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    METHODS OF FORMING SEMICONDUCTOR DIES WITH PERIMETER PROFILES FOR STACKED DIE PACKAGES
    13.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DIES WITH PERIMETER PROFILES FOR STACKED DIE PACKAGES 有权

    公开(公告)号：US20210202318A1

    公开(公告)日：2021-07-01

    申请号：US16896091

    申请日：2020-06-08

    Applicant: Micron Technology, Inc.

    Inventor： Yeongbeom Ko ,  Jong Sik Paek

    IPC: H01L21/78 ,  H01L21/268

    Abstract: The present technology is directed to methods of forming semiconductor dies with rabbeted regions. For example, the method can comprise forming a first channel along a street from a backside of the wafer to an intermediate depth between the backside of the wafer and a front side of the wafer. The first channel has a first sloped sidewall and a second sloped sidewall. A second channel is then formed by laser cutting from the intermediate depth in the wafer toward the front side of the wafer along a region between the first and second sidewalls of the first channel. The first sloped sidewall defines a rabbeted region at a side of the first semiconductor dies and the second sloped sidewall defines a rabbeted region at a side of the second semiconductor dies.

    GROUND CONNECTION FOR SEMICONDUCTOR DEVICE ASSEMBLY
    14.
    发明申请
    GROUND CONNECTION FOR SEMICONDUCTOR DEVICE ASSEMBLY 有权

    公开(公告)号：US20210175182A1

    公开(公告)日：2021-06-10

    申请号：US16706443

    申请日：2019-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Jong Sik Paek ,  Youngik Kwon ,  Yeongbeom Ko

    IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

    Abstract: Semiconductor device assemblies with improved ground connections, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly may include one or more semiconductor dies mounted on an upper surface of a package substrate. Further, the package substrate includes a bond pad disposed on the upper surface, which may be designated as a ground node for the semiconductor device assembly. The bond pad may be electrically connected to an electromagnetic interference (EMI) shield of the semiconductor device assembly through a conductive component attached to the bond pad and configured to be in contact with the EMI shield at a sidewall surface or a top surface of the semiconductor device assembly, thereby forming the ground connection. Such ground connection may reduce a processing time to form the EMI shield while improving yield and reliability performance of the semiconductor device assemblies.

    FACE-TO-FACE SEMICONDUCTOR DEVICE WITH FAN-OUT PORCH
    16.
    发明申请
    FACE-TO-FACE SEMICONDUCTOR DEVICE WITH FAN-OUT PORCH 有权

    公开(公告)号：US20230013960A1

    公开(公告)日：2023-01-19

    申请号：US17952563

    申请日：2022-09-26

    Applicant: Micron Technology, Inc.

    Inventor： Jong Sik Paek ,  Yeongbeom Ko

    IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00

    Abstract: Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.

    Stacked semiconductor dies for semiconductor device assemblies
    17.
    发明授权
    Stacked semiconductor dies for semiconductor device assemblies 有权

    公开(公告)号：US11362071B2

    公开(公告)日：2022-06-14

    申请号：US17001435

    申请日：2020-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Yeongbeom Ko ,  Youngik Kwon ,  Jong Sik Paek ,  Jungbae Lee

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56

    Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

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