公开(公告)号：US11923332B2

公开(公告)日：2024-03-05

申请号：US17552830

申请日：2021-12-16

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/10122 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/26145 ,  H01L2224/73204

Abstract: A semiconductor device having a capillary flow structure for a direct chip attachment is provided herein. The semiconductor device generally includes a substrate and a semiconductor die having a conductive pillar electrically coupled to the substrate. The front side of the semiconductor die may be spaced a distance apart from the substrate forming a gap. The semiconductor device further includes first and second elongate capillary flow structures projecting from the front side of the semiconductor die at least partially extending toward the substrate. The first and second elongate capillary flow structures may be spaced apart from each other at a first width configured to induce capillary flow of an underfill material along a length of the first and second elongate capillary flow structures. The first and second capillary flow structures may include pairs of elongate capillary flow structures forming passageways therebetween to induce capillary flow at an increased flow rate.

公开(公告)号：US11362071B2

公开(公告)日：2022-06-14

申请号：US17001435

申请日：2020-08-24

Applicant: Micron Technology, Inc.

Inventor： Yeongbeom Ko ,  Youngik Kwon ,  Jong Sik Paek ,  Jungbae Lee

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56

Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

公开(公告)号：US11342277B2

公开(公告)日：2022-05-24

申请号：US16897867

申请日：2020-06-10

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L23/552 ,  H01L21/56

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate including an upper surface having a plurality of internal contact pads and at least one grounding pad and a lower surface having a plurality of external contact pads. The assembly further includes a semiconductor die coupled to the plurality of internal contact pads, a conductive underfill dam coupled to the at least one grounding pad, and underfill material disposed at least between the semiconductor die and the substrate. The underfill material includes a fillet between the semiconductor die and the underfill dam. The assembly further includes a conductive EMI shield disposed over the semiconductor die, the fillet, and the conductive underfill dam.

公开(公告)号：US11942455B2

公开(公告)日：2024-03-26

申请号：US17741799

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Yeongbeom Ko ,  Youngik Kwon ,  Jong Sik Paek ,  Jungbae Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/31 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/85

Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

公开(公告)号：US11887938B2

公开(公告)日：2024-01-30

申请号：US17732276

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/563

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate including an upper surface having a plurality of internal contact pads and at least one grounding pad and a lower surface having a plurality of external contact pads. The assembly further includes a semiconductor die coupled to the plurality of internal contact pads, a conductive underfill dam coupled to the at least one grounding pad, and underfill material disposed at least between the semiconductor die and the substrate. The underfill material includes a fillet between the semiconductor die and the underfill dam. The assembly further includes a conductive EMI shield disposed over the semiconductor die, the fillet, and the conductive underfill dam.

公开(公告)号：US20230069208A1

公开(公告)日：2023-03-02

申请号：US17592029

申请日：2022-02-03

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L25/065 ,  H01L25/00

Abstract: Stacked semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device can include a package substrate and a stack of semiconductor dies carried by the package substrate. The stack of semiconductor dies includes a first die carried by the package substrate and a second die carried by the first die. The semiconductor device also includes an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The interconnect module includes a first end coupled the package substrate, a second end opposite the first end, a conductive via extending through a body of organic material from the first end to the second end. The first semiconductor die can is electrically coupled directly to the package substrate, while the second semiconductor die is electrically coupled to the package substrate through the second end of the interconnect module.

公开(公告)号：US11532595B2

公开(公告)日：2022-12-20

申请号：US17190324

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L25/065 ,  H01L25/00

Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with an opening extending therethrough. The assembly can include a stack of semiconductor dies attached to the substrate. The stack includes a first die attached to a front surface of the substrate, where the first die includes a first bond pad aligned with the opening. The stack also includes a second die attached to the first die such that an edge of the second die extends past a corresponding edge of the first die. The second die includes a second bond pad uncovered by the first die and aligned with the opening. A bond wire formed through the opening couples the first and second bond pads with a substrate bond pad on a back surface of the substrate.

公开(公告)号：US20220254732A1

公开(公告)日：2022-08-11

申请号：US17732276

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L23/552 ,  H01L21/56

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate including an upper surface having a plurality of internal contact pads and at least one grounding pad and a lower surface having a plurality of external contact pads. The assembly further includes a semiconductor die coupled to the plurality of internal contact pads, a conductive underfill dam coupled to the at least one grounding pad, and underfill material disposed at least between the semiconductor die and the substrate. The underfill material includes a fillet between the semiconductor die and the underfill dam. The assembly further includes a conductive EMI shield disposed over the semiconductor die, the fillet, and the conductive underfill dam.

公开(公告)号：US20220068666A1

公开(公告)日：2022-03-03

申请号：US17007607

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee ,  Chih Hong Wang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

Abstract: Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.

公开(公告)号：US11621245B2

公开(公告)日：2023-04-04

申请号：US16892084

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Yeongbeom Ko ,  Youngik Kwon ,  Jungbae Lee

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56

Abstract: This patent application relates to microelectronic device packages with internal EMI shielding, methods of fabricating and related electronic systems. One or more microelectronic devices of a package including multiple microelectronic devices are EMI shielded, and one or more other microelectronic devices of the package are located outside the EMI shielding.