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公开(公告)号：US11302377B2
公开(公告)日：2022-04-12
申请号：US16655110
申请日：2019-10-16
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C7/00 , G11C11/406 , G11C29/20
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic targeted refresh steals. A memory bank may receive access commands and then periodically enter a refresh mode, where auto-refresh operations and targeted refresh operations are performed. The memory bank may receive a refresh management command based on a count of access commands directed to the memory bank. Responsive to the refresh management signal, a panic targeted refresh operation may be performed on the memory bank. A number of times the refresh management signal was issued may be counted, and based on that count a next periodic targeted refresh operation may be skipped.
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公开(公告)号：US10943636B1
公开(公告)日：2021-03-09
申请号：US16546152
申请日：2019-08-20
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C7/00 , G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for analog row access tracking. A plurality of unit cells are provided, each of which contains one or more analog circuits used to track accesses to a portion of the wordlines of a memory device. When a wordline in the portion is accessed, the unit cell may update an accumulator voltage, for example by adding charge to a capacitor. A comparator circuit may determine when one or more accumulator voltages cross a threshold (e.g., a reference voltage). Responsive to the accumulator voltage crossing the threshold, an aggressor address may be loaded in a targeted refresh queue, or if the aggressor address is already in the queue, a priority flag associated with that address may be set. Aggressor addresses may be provided to have their victims refreshed in an order based on the number of set priority flags.
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公开(公告)号：US10447316B2
公开(公告)日：2019-10-15
申请号：US14423343
申请日：2014-12-19
Applicant: Micron Technology, Inc.
Inventor： Wei Bing Shang , Yu Zhang , Hong Wen Li , Yu Peng Fan , Zhong Lai Liu , En Peng Gao , Liang Zhang
Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
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公开(公告)号：US09148176B2
公开(公告)日：2015-09-29
申请号：US14002092
申请日：2013-06-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yu Zhang , Wei Bing Shang , En Peng Gao
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/1048 , G11C29/42 , G11C2029/0411 , H03M13/2942 , H03M13/6561
Abstract: One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. The apparatus also includes a second circuit configured to also receive the first and second data words, to preliminarily merge the first and second data words responsive to the control signal to generate an initial merged data word, to generate an initial parity code for the initial merged data word, to correct the initial parity code, and to provide the corrected parity code to the write circuit.
Abstract translation: 一个示例性设备包括：第一电路，被配置为接收第一和第二数据字，以校正第一数据字中的一个或多个错误，以响应于控制信号合并校正的第一数据字和第二数据字，以产生最终合并 数据字，并将最终合并的数据字提供给写入电路。 该装置还包括配置为还接收第一和第二数据字的第二电路，以响应于控制信号预先合并第一和第二数据字以产生初始合并数据字，以产生用于初始合并的初始奇偶校验码 数据字，以校正初始奇偶校验码，并将校正的奇偶校验码提供给写电路。
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公开(公告)号：US11715512B2
公开(公告)日：2023-08-01
申请号：US17654035
申请日：2022-03-08
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C7/00 , G11C11/406 , G11C29/20
CPC classification number: G11C11/40622 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C29/20
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic targeted refresh steals. A memory bank may receive access commands and then periodically enter a refresh mode, where auto refresh operations and targeted refresh operations are performed. The memory bank may receive a refresh management command based on a count of access commands directed to the memory bank. Responsive to the refresh management signal, a panic targeted refresh operation may be performed on the memory bank. A number of times the refresh management signal was issued may be counted, and based on that count a next periodic targeted refresh operation may be skipped.
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Patent Agency Ranking
公开(公告)号：US20220059158A1
公开(公告)日：2022-02-24
申请号：US16997659
申请日：2020-08-19
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C11/408 , G11C11/4091 , G11C11/4096
Abstract: Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.
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公开(公告)号：US11152078B1
公开(公告)日：2021-10-19
申请号：US17005579
申请日：2020-08-28
Applicant: MICRON TECHNOLOGY, INC.
Abstract: Embodiments of the disclosure are drawn to apparatuses methods for checking redundancy information for row addresses prior to performing various refresh operations, such as auto refresh and targeted refresh operations. In some examples, refresh operations may be multi pump refresh operations. In some examples, a targeted refresh operation may be performed prior to an auto refresh operation responsive to a multi pump refresh operation. In some examples, redundancy information for the auto refresh operation may be performed, at least in part, during the targeted refresh operation. In some examples, refresh operations on word lines may be skipped when the redundancy information indicates the word line is defective or unused.
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公开(公告)号：US20210118491A1
公开(公告)日：2021-04-22
申请号：US16655110
申请日：2019-10-16
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C29/20
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic targeted refresh steals. A memory bank may receive access commands and then periodically enter a refresh mode, where auto-refresh operations and targeted refresh operations are performed. The memory bank may receive a refresh management command based on a count of access commands directed to the memory bank. Responsive to the refresh management signal, a panic targeted refresh operation may be performed on the memory bank. A number of times the refresh management signal was issued may be counted, and based on that count a next periodic targeted refresh operation may be skipped.
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19.发明申请APPARATUSES AND METHODS FOR PIPELINING MEMORY OPERATIONS WITH ERROR CORRECTION CODING 审中-公开用于管理具有错误校正编码的存储器操作的装置和方法公开(公告)号：US20160315639A1
公开(公告)日：2016-10-27
申请号：US14423343
申请日：2014-12-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Wei Bing Shang , Yu Zhang , Hong Wen Li , Yu Peng Fan , Zhong Lai Liu , En Peng Gao , Liang Zhang
Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
Abstract translation: 公开了用于通过纠错编码流水线存储器操作的装置和方法。 公开了一种用于流水线连续写入掩模操作的方法，其中在第一写入掩码操作的纠错码计算期间发生第二写入掩模操作的第二读取操作。 该方法还可以包括在第二写入掩码操作的纠错码计算期间从第一写入掩码操作中写入数据。 公开了一种用于流水线连续操作的方法，其中如果第一操作不是写掩码操作，则可以取消第一读取操作。 公开了一种包括具有单独的全局读和写输入 - 输出线的存储器的装置。
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公开(公告)号：US11955991B2
公开(公告)日：2024-04-09
申请号：US17723277
申请日：2022-04-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Wei Bing Shang , Yu Zhang , Hong Wen Li , Yu Peng Fan , Zhong Lai Liu , En Peng Gao , Liang Zhang
CPC classification number: H03M13/45 , G06F9/38 , G06F11/1048 , H03M13/611
Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
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