公开(公告)号：US20230039910A1

公开(公告)日：2023-02-09

申请号：US17967721

申请日：2022-10-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F9/4401 ,  G06N3/04 ,  G06F9/445 ,  G06N3/08 ,  G06F12/06

Abstract: In a mobile device, processes of an application can be monitored and scored for initial data distribution. Specifically, a method can include monitoring processes of an application, and scoring objects or components used by the processes to determine placement of the objects or components in memory during initiation of the application. The method can also include, during initiation of the application, loading, into a first portion of the memory, at least partially, the objects or components scored at a first level. The method can also include, during initiation of the application, loading, into a second portion of the memory, at least partially, the objects or components scored at a second level. The objects or components scored at the second level can be less critical to the application than the objects or components scored at the first level.

公开(公告)号：US20220413900A1

公开(公告)日：2022-12-29

申请号：US17898642

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F9/48 ,  G06F9/38 ,  G11C11/409 ,  G06F11/34 ,  G06F11/30

Abstract: Customized root processes for groups of applications in a computing device. A computing device (e.g., a mobile device) can monitor usage of applications. The device can then store data related to the usage of the applications, and group the applications into groups according to the stored data. The device can customize and execute a root process for a group of applications according to usage common to each application in the group. The device can generate patterns of prior executions shared amongst the applications in the group based on the stored data common to each application in the group, and execute the root process of the group according to the patterns. The device can receive a request to start an application from the group from a user of the device, and start the application upon receiving the request and by using the root process of the group of applications.

公开(公告)号：US11355170B1

公开(公告)日：2022-06-07

申请号：US17123829

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G11C8/06 ,  G11C8/08 ,  H03K19/017

Abstract: An example system implementing a processing-in-memory pipeline includes: a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; a logic array coupled to the memory array, the logic array to implement configurable logic controlling the plurality of memory cells; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.

公开(公告)号：US20210406176A1

公开(公告)日：2021-12-30

申请号：US17469090

申请日：2021-09-08

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F12/06 ,  G06F12/0877 ,  G11C11/4091 ,  G11C11/4094 ,  G06F13/16

Abstract: An apparatus having a memory array. The memory array having a first section and a second section. The first section of the memory array including a first sub-array of memory cells made up of a first type of memory. The second section of the memory array including a second sub-array of memory cells made up of the first type of memory with a configuration to each memory cell of the second sub-array that is different from the configuration to each cell of the first sub-array. Alternatively, the section can include memory cells made up of a second type of memory that is different from the first type of memory. Either way, the second type of memory or the differently configured first type of memory has memory cells in the second sub-array having less memory latency than each memory cell of the first type of memory in the first sub-array.

公开(公告)号：US11169930B2

公开(公告)日：2021-11-09

申请号：US16424427

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert

IPC: G06F12/1009 ,  G06F12/1027 ,  G06N5/04 ,  H04L29/08 ,  H04W8/26

Abstract: Systems, methods and apparatuses of fine grain data migration in using Memory as a Service (MaaS) are described. For example, a memory status map can be used to identify the cache availability of sub-regions (e.g., cache lines) of a borrowed memory region (e.g., a borrowed remote memory page). Before accessing a virtual memory address in a sub-region, the memory status map is checked. If the sub-region has cache availability in the local memory, the memory management unit uses a physical memory address converted from the virtual memory address to make memory access. Otherwise, the sub-region is cached from the borrowed memory region to the local memory, before the physical memory address is used.

公开(公告)号：US20210294746A1

公开(公告)日：2021-09-23

申请号：US16824621

申请日：2020-03-19

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F12/0873 ,  G06F12/0846 ,  G06F12/02 ,  G06F12/1009 ,  G06F9/54

Abstract: A memory module system with a global shared context. A memory module system can include a plurality of memory modules and at least one processor, which can implement the global shared context. The memory modules of the system can provide the global shared context at least in part by providing an address space shared between the modules and applications running on the modules. The address space sharing can be achieved by having logical addresses global to the modules, and each logical address can be associated with a certain physical address of a specific module.

公开(公告)号：US20210294741A1

公开(公告)日：2021-09-23

申请号：US16824618

申请日：2020-03-19

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F12/06 ,  G06F12/0877 ,  G06F13/16 ,  G11C11/4091 ,  G11C11/4094

Abstract: An apparatus having a memory array. The memory array having a first section and a second section. The first section of the memory array including a first sub-array of memory cells made up of a first type of memory. The second section of the memory array including a second sub-array of memory cells made up of the first type of memory with a configuration to each memory cell of the second sub-array that is different from the configuration to each cell of the first sub-array. Alternatively, the section can include memory cells made up of a second type of memory that is different from the first type of memory. Either way, the second type of memory or the differently configured first type of memory has memory cells in the second sub-array having less memory latency than each memory cell of the first type of memory in the first sub-array.

公开(公告)号：US11100007B2

公开(公告)日：2021-08-24

申请号：US16424420

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/1027 ,  H04L29/08 ,  H04W84/04

Abstract: Systems, methods and apparatuses to accelerate accessing of borrowed memory over network connection are described. For example, a memory management unit (MMU) of a computing device can be configured to be connected both to the random access memory over a memory bus and to a computer network via a communication device. The computing device can borrow an amount of memory from a remote device over a network connection using the communication device; and applications running in the computing device can use virtual memory addresses mapped to the borrowed memory. When a virtual address mapped to the borrowed memory is used, the MMU translates the virtual address into a physical address and instruct the communication device to access the borrowed memory.

公开(公告)号：US20210072957A1

公开(公告)日：2021-03-11

申请号：US16888345

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Dmitri Yudanov ,  Sivagnanam Parthasarathy

IPC: G06F7/544 ,  G06F17/16

Abstract: Systems, apparatuses, and methods of operating memory systems are described. Processing-in-memory capable memory devices are also described, and methods of performing fused-multiply-add operations within the same. Bit positions of bits stored at one or more portions of one or more memory arrays, may be accessed via data lines by activating the same or different access lines. A sensing circuit operatively coupled to a data line may be temporarily formed and measured to determine a state (e.g., a count of the number of bits that are a logic “1”) of accessed bit positions of a data line, and state information may be used to determine a computational result.

公开(公告)号：US20240290391A1

公开(公告)日：2024-08-29

申请号：US18417899

申请日：2024-01-19

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Jeongsu Jeong

IPC: G11C16/12

CPC classification number: G11C16/12

Abstract: A system for providing complex page access in memory devices, such as hybrid-bonded memory is disclosed. The system receives a plurality of requests for data, such as from a host device. The system identifies a memory page of a memory device storing data bits corresponding to the requested data. The memory page may be spread across a plurality of sections of a memory bank of the memory device. Each section of the memory bank being utilized for a portion of the memory page may be addressable by a separate row address. The system activates the memory page as a whole and enables the data to be accessed from different memory rows in different sections of the memory page of the memory device using the separate row addresses. The system accomplishes the foregoing instead of requiring access from only a single location of the memory bank at a time.