公开(公告)号：US20110239046A1

公开(公告)日：2011-09-29

申请号：US12748455

申请日：2010-03-29

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： G06F11/263

CPC分类号： G11C29/022 ,  G11C29/1201

摘要： The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1≦i≦M. The jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1≦j≦M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.

摘要翻译： 本发明提供了一种用于n个输入/输出阵列的测试电路。 n个输入/输出阵列中的每一个具有M对输入/输出。 测试电路包括M个写入驱动器和M个比较电路。 第i个写入驱动器向所有n个输入/输出阵列的第i个输入提供第i个测试信号，1＆nlE; i＆nlE; M。 第j个比较电路确定所有n个输入/输出阵列的第j个输出信号是否相同，并相应地输出第j个比较结果，并且1＆nlE; j＆nlE; M。 本发明还提供了一种测试n个输入/输出阵列的方法。 本发明还提供一种存储装置。

公开(公告)号：US07787536B2

公开(公告)日：2010-08-31

申请号：US11742316

申请日：2007-04-30

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： H03H7/30

CPC分类号： H04L25/03006 ,  H04L1/20 ,  H04L7/0331 ,  H04L2025/03356 ,  H04L2025/03611

摘要： An adaptive equalizer apparatus with digital eye-opening monitor unit and the method thereof are provided. The apparatus comprises an equalizer unit, a sampling unit, and an eye-opening monitor unit. The equalizer unit equalizes a first signal to a second signal. The sampling unit over-samples the second signal and determines the logic status of the second signal according to the sampling data. The eye-opening monitor unit processes the sampling data and outputs a detecting signal according to the processing result. The detecting signal represents the adequacy of the parameters of the equalizer unit, and the equalizer unit determines whether to change its parameters according to the detecting signal.

摘要翻译： 提供一种具有数字开眼监测单元的自适应均衡器及其方法。 该装置包括均衡器单元，采样单元和开眼监视单元。 均衡器单元将第一信号与第二信号相等。 采样单元对第二信号进行超采样，并根据采样数据确定第二信号的逻辑状态。 开眼监视器单元处理采样数据并根据处理结果输出检测信号。 检测信号表示均衡器单元的参数的适当性，并且均衡器单元根据检测信号确定是否改变其参数。

公开(公告)号：US07432758B2

公开(公告)日：2008-10-07

申请号：US11557503

申请日：2006-11-08

申请人： Min-Chung Chou ,  Tse-Hua Yao

发明人： Min-Chung Chou ,  Tse-Hua Yao

IPC分类号： G05F3/02

CPC分类号： G05F1/56

摘要： A voltage regulator as a stable power supply to internal circuits in a semiconductor memory device is provided. This regulator includes a comparing unit, a first driver transistor, a feedback unit, an auxiliary control unit, a first switch, a second switch, and a second driver transistor. The comparing unit compares a reference voltage with a feedback signal to control the first driver transistor and maintain the internal power supply at a stable level. The second driver transistor, controlled by the first and second switches responsive to a trigger signal corresponding abrupt current consumptions and the auxiliary control unit responsive to the comparing result, supplies sufficient and appropriate current to the internal circuits and prevents the internal power supply from excessive overshoot and drop-out.

摘要翻译： 提供了一种稳压器作为半导体存储器件内部电路的稳定电源。 该调节器包括比较单元，第一驱动晶体管，反馈单元，辅助控制单元，第一开关，第二开关和第二驱动晶体管。 比较单元将参考电压与反馈信号进行比较，以控制第一驱动晶体管并将内部电源维持在稳定的水平。 响应于对应于突发电流消耗的触发信号由控制的第一和第二开关的第二驱动晶体管和响应于比较结果的辅助控制单元向内部电路提供足够和适当的电流并防止内部电源过度过冲 和辍学。

公开(公告)号：US20080122415A1

公开(公告)日：2008-05-29

申请号：US11557503

申请日：2006-11-08

申请人： Min-Chung Chou ,  Tse-Hua Yao

发明人： Min-Chung Chou ,  Tse-Hua Yao

IPC分类号： G05F1/44 ,  G05F1/02

CPC分类号： G05F1/56

摘要： A voltage regulator as a stable power supply to internal circuits in a semiconductor memory device is provided. This regulator includes a comparing unit, a first driver transistor, a feedback unit, an auxiliary control unit, a first switch, a second switch, and a second driver transistor. The comparing unit compares a reference voltage with a feedback signal to control the first driver transistor and maintain the internal power supply at a stable level. The second driver transistor, controlled by the first and second switches responsive to a trigger signal corresponding abrupt current consumptions and the auxiliary control unit responsive to the comparing result, supplies sufficient and appropriate current to the internal circuits and prevents the internal power supply from excessive overshoot and drop-out.

摘要翻译： 提供了一种稳压器作为半导体存储器件内部电路的稳定电源。 该调节器包括比较单元，第一驱动晶体管，反馈单元，辅助控制单元，第一开关，第二开关和第二驱动晶体管。 比较单元将参考电压与反馈信号进行比较，以控制第一驱动晶体管并将内部电源维持在稳定的水平。 响应于对应于突发电流消耗的触发信号由控制的第一和第二开关的第二驱动晶体管和响应于比较结果的辅助控制单元向内部电路提供足够和适当的电流并防止内部电源过度过冲 和辍学。

公开(公告)号：US20060050599A1

公开(公告)日：2006-03-09

申请号：US11250073

申请日：2005-10-13

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： G11C8/02

CPC分类号： G11C29/12005 ,  G11C11/401 ,  G11C29/006 ,  G11C29/12 ,  G11C2029/1202

摘要： A memory device and a method for burn-in test are described. The memory device has a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line current value. In burn-in test mode, the output of a word line driver is kept in a high impedance state. The bit line stress voltage is applied to the row of memory cells through a normal read-write path. A voltage generator for generating a substantially stable voltage is also provided. In burn-in test mode, the even word lines and the odd word lines are grouped separately and the word line stress voltage is applied to the even word lines and to the odd word lines alternately.

摘要翻译： 描述了用于老化测试的存储器件和方法。 存储器件具有多个子阵列字线泄漏限制单元和多个单个字线泄漏电流限制单元。 它们用于将每个字线中的电流限制为预定的字线电流值。 在老化测试模式下，字线驱动器的输出保持在高阻抗状态。 位线应力电压通过正常读写路径施加到存储单元行。 还提供了用于产生基本上稳定的电压的电压发生器。 在老化测试模式下，偶数字线和奇数字线被分开分组，并且字线应力电压交替地施加到偶数字线和奇数字线。

公开(公告)号：US06298003B1

公开(公告)日：2001-10-02

申请号：US09758931

申请日：2001-01-11

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： G11C800

CPC分类号： G11C7/22 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085

摘要： A boost circuit for driving word lines in a memory device, comprises: a delaying module for delaying signal to turn on a refresh cycle of the boost circuit; a precharge timing controlling module for controlling the timing of the refresh cycle, wherein the delay module transmitting the signal to the precharge timing controlling module for disabling and enabling the precharge timing controlling module; a precharge module for supplying charge to a first capacitor and a second capacitor, wherein the precharge module is controlled by the precharge timing controlling module; a first capacitor connected to the precharge module and charge the word lines for storing charges; when the precharge module stops to charge the first capacitor, the first capacitor starts to charge the word lines in 2k refresh mode and charge both of the word lines and the second capacitor in 4k refresh mode of the memory device; a second capacitor connected to the precharge module and charge the word lines for storing charges, wherein the second capacitor is connected to a controlling module for deciding to turn on the second capacitor, when the precharge module stops to charge the second capacitor, the second capacitor starts to charge the word lines in 2k refresh mode, but in 4k refresh mode of the memory device the first capacitor starts to charge the second capacitor and the word lines together.

摘要翻译： 一种用于驱动存储器件中的字线的升压电路，包括：延迟模块，用于延迟信号以导通升压电路的刷新周期; 预充电定时控制模块，用于控制刷新周期的定时，其中所述延迟模块将所述信号发送到所述预充电定时控制模块，用于禁用并使能所述预充电定时控制模块; 预充电模块，用于向第一电容器和第二电容器提供电荷，其中预充电模块由预充电定时控制模块控制; 连接到预充电模块的第一电容器，并对字线充电以存储电荷; 当预充电模块停止对第一电容器充电时，第一电容器以2k刷新模式开始对字线充电，并且在存储器件的4k刷新模式下对字线和第二电容器充电; 连接到预充电模块的第二电容器，并对用于存储电荷的字线充电，其中当预充电模块停止向第二电容器充电时，第二电容器连接到用于决定接通第二电容器的控制模块，第二电容器 开始在2k刷新模式下对字线充电，但是在存储器件的4k刷新模式下，第一个电容器开始对第二个电容器和字线充电。

公开(公告)号：US08296611B2

公开(公告)日：2012-10-23

申请号：US12748455

申请日：2010-03-29

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： G11C29/00 ,  H03M13/00

CPC分类号： G11C29/022 ,  G11C29/1201

摘要： The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1≦i≦M. The jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1≦j≦M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.

摘要翻译： 本发明提供了一种用于n个输入/输出阵列的测试电路。 n个输入/输出阵列中的每一个具有M对输入/输出。 测试电路包括M个写入驱动器和M个比较电路。 第i个写入驱动器为所有n个输入/输出阵列的第i个输入提供第i个测试信号，并且1＆nlE; i＆nlE; M。 第j个比较电路确定所有n个输入/输出阵列的第j个输出信号是否相同，并相应地输出第j个比较结果，并且1＆nlE; j＆nlE; M。 本发明还提供了一种测试n个输入/输出阵列的方法。 本发明还提供一种存储装置。

公开(公告)号：US08238139B2

公开(公告)日：2012-08-07

申请号：US12748453

申请日：2010-03-29

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： G11C11/4063 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096

CPC分类号： G11C11/4091 ,  G11C11/4096 ,  G11C2207/002

摘要： A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage source. The second inverter receives a second driving signal output from the first inverter. A power end of the second inverter is coupled to a second voltage source. The sense amplifier senses and amplifies a voltage difference between a first sensing signal and a second sensing signal. A power end of the sense amplifier is coupled to a third voltage source, wherein a voltage value of the second voltage source is between a voltage value of the first voltage source and a voltage value of the third voltage source.

摘要翻译： 一种动态RAM，其包括第一反相器，第二反相器，读出放大器，第一对开关，一对位线和动态RAM单元。 第一反相器接收第一驱动信号。 第一反相器的电源端耦合到第一电压源。 第二反相器接收从第一反相器输出的第二驱动信号。 第二反相器的电源端耦合到第二电压源。 感测放大器感测并放大第一感测信号和第二感测信号之间的电压差。 读出放大器的电源端耦合到第三电压源，其中第二电压源的电压值在第一电压源的电压值和第三电压源的电压值之间。

公开(公告)号：US08107307B2

公开(公告)日：2012-01-31

申请号：US12699905

申请日：2010-02-04

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： G11C7/00

CPC分类号： G11C7/10 ,  G11C8/00

摘要： A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression module for compressing the data from the memory array banks to the bus. The second data path transmits the data from the memory array banks to the bus. The third data path includes a second compression module for compressing data from the bus to the data buffer. The fourth data path transmits the data from the bus to the data buffer.

摘要翻译： 提供存储器件。 存储器件包括多个存储器阵列组，总线，数据缓冲器和四个数据路径。 数据缓冲区将数据从存储器阵列组提供给外部节点。 第一数据路径包括用于将数据从存储器阵列组压缩到总线的第一压缩模块。 第二数据路径将数据从存储器阵列发送到总线。 第三数据路径包括用于将数据从总线压缩到数据缓冲器的第二压缩模块。 第四数据路径将数据从总线传送到数据缓冲器。

公开(公告)号：US20100172400A1

公开(公告)日：2010-07-08

申请号：US12350193

申请日：2009-01-07

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： H03K5/159 ,  H04L7/02

CPC分类号： H04L7/0058 ,  H03K9/08 ,  H04L25/03019

摘要： An adaptive equalization apparatus is provided. The adaptive equalization apparatus includes an equalizer, a monitor circuit, and a control circuit. The equalizer receives a first signal, and equalizes the first signal according to an equalization parameter setting to thereby generate a second signal. The monitor circuit is electrically connected to the equalizer, and monitors edges of the second signal in a real-time manner to thereby generate a detection result. The control logic is electrically connected to the equalizer, and adaptively adjusts the equalization parameter setting according to the detection result.

摘要翻译： 提供一种自适应均衡装置。 自适应均衡装置包括均衡器，监视电路和控制电路。 均衡器接收第一信号，并根据均衡参数设置对第一信号进行均衡，从而产生第二信号。 监视电路电连接到均衡器，并且以实时的方式监视第二信号的边缘，从而产生检测结果。 控制逻辑电连接到均衡器，并且根据检测结果自适应地调整均衡参数设置。