公开(公告)号：US5777906A

公开(公告)日：1998-07-07

申请号：US660145

申请日：1996-06-07

申请人： Hon Shing Lau ,  Le Tieu Ly

发明人： Hon Shing Lau ,  Le Tieu Ly

IPC分类号： G06F5/01 ,  G06F7/00

CPC分类号： G06F5/01 ,  G06F7/4991

摘要： An integrated circuit including a circuit for determining shift overflow in a binary digital circuit having an n-bit shift data and an m-bit shift amount. The device has a logic array for producing an n-bit output from the m-bit shift amount; a conversion circuit for selectively converting the sign of an n-bit shift data; and a combination of OR and AND logical gates for logically combining the selectively converted n-bit shift data and the n-bit output producing an overflow output.

摘要翻译： 一种集成电路，包括用于确定具有n位移位数据和m位移位量的二进制数字电路中的移位溢出的电路。 该器件具有用于从m位移位量产生n位输出的逻辑阵列; 用于选择性地转换n位移位数据的符号的转换电路; 以及用于逻辑地组合选择性转换的n位移位数据和产生溢出输出的n位输出的OR和AND逻辑门的组合。

公开(公告)号：US08604603B2

公开(公告)日：2013-12-10

申请号：US12709291

申请日：2010-02-19

申请人： Hon Shing Lau ,  Shi-Wei Lee ,  Matthew Ming Fai Yuen ,  Jingshen Wu ,  Chi Chuen Lo ,  Haibo Fan ,  Haibin Chen

发明人： Hon Shing Lau ,  Shi-Wei Lee ,  Matthew Ming Fai Yuen ,  Jingshen Wu ,  Chi Chuen Lo ,  Haibo Fan ,  Haibin Chen

IPC分类号： H01L29/72

CPC分类号： H01L23/5384 ,  H01L23/055 ,  H01L23/433 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat.

摘要翻译： 本文描述了具有三维集成电路结构的装置。 该装置包括用于承载多个高功率和低功率芯片的插入器。 高功率芯片被连接并连接到插入器的一侧，而低功率芯片被附接并连接到插入器的另一侧。 一般来说，高功率芯片在运行时产生比低功率芯片更多的热量。 插入器还包括通过硅通孔和用于连接两个表面上的芯片的再分配层。 此外，插入器组件附接并连接到衬底层，衬底层又连接并连接到印刷电路板。 为了提供改进的热管理，承载大功率芯片的插入器表面远离电路板。 散热器附着在大功率芯片的背面以散热。

公开(公告)号：US20100213600A1

公开(公告)日：2010-08-26

申请号：US12709291

申请日：2010-02-19

申请人： Hon Shing Lau ,  Shi-Wei Lee ,  Matthew Ming Fai Yuen ,  Jingshen Wu ,  Chi Chuen Lo ,  Haibo Fan ,  Haibin Chen

发明人： Hon Shing Lau ,  Shi-Wei Lee ,  Matthew Ming Fai Yuen ,  Jingshen Wu ,  Chi Chuen Lo ,  Haibo Fan ,  Haibin Chen

IPC分类号： H01L23/34 ,  H01L21/60 ,  H01L23/498

CPC分类号： H01L23/5384 ,  H01L23/055 ,  H01L23/433 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat.

摘要翻译： 本文描述了具有三维集成电路结构的装置。 该装置包括用于承载多个高功率和低功率芯片的插入器。 高功率芯片被连接并连接到插入器的一侧，而低功率芯片被附接并连接到插入器的另一侧。 一般来说，高功率芯片在运行时产生比低功率芯片更多的热量。 插入器还包括通过硅通孔和用于连接两个表面上的芯片的再分配层。 此外，插入器组件附接并连接到衬底层，衬底层又连接并连接到印刷电路板。 为了提供改进的热管理，承载大功率芯片的插入器表面远离电路板。 散热器附着在大功率芯片的背面以散热。

公开(公告)号：US5920493A

公开(公告)日：1999-07-06

申请号：US912046

申请日：1997-08-15

申请人： Hon Shing Lau

发明人： Hon Shing Lau

IPC分类号： G06F7/00 ,  G06F7/50 ,  G06F7/74 ,  G06F7/38

CPC分类号： G06F7/74 ,  G06F7/485 ,  G06F7/49936

摘要： An adder using a leading zero/one detector (LZD) circuit and method of use determine an exact normalization shift with fewer logic levels and number of gates, resulting in saving considerable execution time to improve not only the timing as well as to reduce the size of the logic implementing the adder. In addition, a parallel method to locate the most significant digit is disclosed. Such an LZD circuit and method may be incorporated in an integrated circuit, and the LZD circuit includes a propagation value generator for generating a propagation value from input signals representing operands; and a location value generator for generating the location value from the generated propagation value.

摘要翻译： 使用前导零/一检测器（LZD）电路和使用方法的加法器使用更少的逻辑电平和门数来确定准确的归一化移位，从而节省大量的执行时间，以便不仅改进定时以及减小时间 的逻辑实现加法器。 此外，公开了一种用于定位最高有效位的并行方法。 这种LZD电路和方法可以并入集成电路中，LZD电路包括传播值发生器，用于从表示操作数的输入信号产生传播值; 以及位置值发生器，用于从所生成的传播值生成位置值。

公开(公告)号：US5838602A

公开(公告)日：1998-11-17

申请号：US712532

申请日：1996-09-11

申请人： Ronald L. Feiller ,  Hon Shing Lau ,  Le Tieu Ly

发明人： Ronald L. Feiller ,  Hon Shing Lau ,  Le Tieu Ly

IPC分类号： G06F7/50 ,  G06F7/507

CPC分类号： G06F7/507

摘要： An integrated circuit having a fast carry generation adder for adding together two input signals has an initial stage and two or more intermediate stages. The adder may also include a final stage. Each intermediate stage has a carry mux and these carry muxes are grouped together, for example, adjacent to the initial stage and adjacent to the first intermediate stage. By grouping the carry muxes together, for example, in a column below the initial stage, the fast carry generation adder may be both faster and smaller than conventional adders and may reduce or even eliminate the need for any buffering between successive carry muxes.

摘要翻译： 具有用于将两个输入信号相加在一起的快速进位产生加法器的集成电路具有初始阶段和两个或更多个中间阶段。 加法器还可以包括最后级。 每个中间级具有进位多路复用器，并且这些进位复用器被分组在一起，例如，与初始阶段相邻并且与第一中间阶段相邻。 通过将进位复用器组合在一起，例如，在初始阶段以下的列中，快速进位生成加法器可以比常规加法器更快和更小，并且可以减少甚至消除对连续的进位复用器之间的任何缓冲的需要。