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    3D semiconductor device, structure and methods
    12.
    发明授权
    3D semiconductor device, structure and methods 有权

    公开(公告)号：US11502095B2

    公开(公告)日：2022-11-15

    申请号：US16649660

    申请日：2018-09-23

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

    IPC: H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538 ,  H01L23/66 ,  H01L27/11582

    Abstract: A 3D device, the device including: at least a first level including logic circuits; at least a second level including an array of memory cells; at least a third level including special circuits; and at least a fourth level including special connectivity structures, where the special connectivity structures include one of the following: a. waveguides, or b. differential signaling, or c. radio frequency transmission lines, or d. Surface Waves Interconnect (SWI) lines, and where the third level includes Radio Frequency (“RF”) circuits to drive the special connectivity structures, where the second level overlays the first level, where the third level overlays the second level, and where the fourth level overlays the third level.

    3D memory semiconductor devices and structures
    13.
    发明授权
    3D memory semiconductor devices and structures 有权

    公开(公告)号：US10892016B1

    公开(公告)日：2021-01-12

    申请号：US16836659

    申请日：2020-03-31

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11582

    Abstract: A method to operate a 3D semiconductor charge trap memory device, the method comprising; executing a memory set-up operation, wherein said memory set-up operation comprises a preload of a plurality of memory cells followed by a partial erase; and then executing a memory operation on said memory cells, wherein each memory cell of said plurality of memory cells comprises a charge trap layer, wherein said memory operation comprises first writing a first memory state by loading a charge into said charge trap layer, and then second writing a second memory state by removing said charge to a partially erased state. Various 3D devices, processing flows and methods are also disclosed.

    United states 3D memory semiconductor devices and structures with memory cells
    14.
    发明授权
    United states 3D memory semiconductor devices and structures with memory cells 有权

    公开(公告)号：US12225727B2

    公开(公告)日：2025-02-11

    申请号：US18738967

    申请日：2024-06-10

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

    Abstract: A 3D memory device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of latch sense amplifiers, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

    3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH BIT-LINE PILLARS
    19.
    发明申请
    3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH BIT-LINE PILLARS 有权

    公开(公告)号：US20230018701A1

    公开(公告)日：2023-01-19

    申请号：US17948225

    申请日：2022-09-20

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: G11C7/18 ,  G11C7/12 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11578

    Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the device includes a temperature sensor.

    3D memory semiconductor devices and structures
    20.
    发明授权
    3D memory semiconductor devices and structures 有权

    公开(公告)号：US11296106B2

    公开(公告)日：2022-04-05

    申请号：US17484394

    申请日：2021-09-24

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: H01L27/11578 ,  H01L27/11573

    Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented; and a level of memory control circuits, where the memory control circuits is disposed either above or below the plurality of memory cells.

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