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    Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device
    11.
    发明授权
    Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device 失效
    图形地址重映射表条目功能标志，用于自定义与加速图形端口设备关联的内存页面的操作

    公开(公告)号：US5999198A

    公开(公告)日：1999-12-07

    申请号：US925772

    申请日：1997-09-09

    申请人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

    发明人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

    IPC分类号： G06F3/14 ,  G06F12/08 ,  G09G5/393 ,  G06F15/16

    CPC分类号： G06F3/14 ,  G06F12/0875 ,  G09G5/393 ,  G09G2360/121

    摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

    摘要翻译： 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器页面的基址的地址指针，以及可用于定制关联的存储器页面的特征标志。

    Accelerated Graphics Port two level Gart cache having distributed first level caches
    12.
    发明授权
    Accelerated Graphics Port two level Gart cache having distributed first level caches 失效
    加速图形端口具有分布式一级高速缓存的两级Gart缓存

    公开(公告)号：US5905509A

    公开(公告)日：1999-05-18

    申请号：US941860

    申请日：1997-09-30

    申请人： Phillip M. Jones ,  Robert Allan Lester ,  Kenneth Tom Chin

    发明人： Phillip M. Jones ,  Robert Allan Lester ,  Kenneth Tom Chin

    IPC分类号： G06F12/10 ,  G06F13/14 ,  G06F12/08

    CPC分类号： G06F12/1027 ,  G06F12/1081 ,  G06F2212/681

    摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset caches a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. The core logic chipset uses a two-level GART cache comprising a plurality of first-level GART caches and a common second level GART cache. Each of the plurality of first-level GART caches are coupled to a respective interface in the computer system and effectively de-couple the different interface GART address translations so that GART cache thrashing and cache arbitration delays are substantially reduced. Separate decoupled first-level GART caches for each interface allow concurrent GART address translations among the different interfaces. Individual first-level GART caches may be fined tuned for each associated interface.

    摘要翻译： 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联页面的特征标记。 核心逻辑芯片组缓存最近使用的GART表项的子集，以在执行地址转换时增加AGP性能。 核心逻辑芯片组使用包括多个第一级GART高速缓存和公共第二级GART高速缓存的双级GART缓存。 多个第一级GART高速缓存中的每一个耦合到计算机系统中的相应接口，并且有效地解耦不同的接口GART地址转换，使得GART高速缓存颠簸和高速缓存仲裁延迟显着降低。 对于每个接口，单独的解耦第一级GART缓存允许在不同接口之间进行并发GART地址转换。 单个第一级GART缓存可能会针对每个相关联的接口进行调整。

    Buffer management structure with selective flush
    13.
    发明授权
    Buffer management structure with selective flush 有权
    具有选择性冲洗的缓冲区管理结构

    公开(公告)号：US08117420B2

    公开(公告)日：2012-02-14

    申请号：US12187986

    申请日：2008-08-07

    申请人： Jian Shen ,  Robert Allan Lester

    发明人： Jian Shen ,  Robert Allan Lester

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1027 ,  Y02D10/13

    摘要： A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.

    摘要翻译： 描述了用于处理系统的缓冲器管理结构。 在一个实施例中，缓冲器管理结构包括存储模块和控制模块。 存储模块包括读取位置，并且可以在写入条目中存储指示事务请求的有效状态的位。 控制模块可以接收无效请求并修改该位以指示事务请求的无效状态，并且当事务请求处于读取位置时丢弃事务请求。

    Buffer Management Structure with Selective Flush
    14.
    发明申请
    Buffer Management Structure with Selective Flush 有权
    缓冲管理结构与选择性冲洗

    公开(公告)号：US20100037028A1

    公开(公告)日：2010-02-11

    申请号：US12187986

    申请日：2008-08-07

    申请人： Jian Shen ,  Robert Allan Lester

    发明人： Jian Shen ,  Robert Allan Lester

    IPC分类号： G06F12/02

    CPC分类号： G06F12/1027 ,  Y02D10/13

    摘要： A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.

    摘要翻译： 描述了用于处理系统的缓冲器管理结构。 在一个实施例中，缓冲器管理结构包括存储模块和控制模块。 存储模块包括读取位置，并且可以在写入条目中存储指示事务请求的有效状态的位。 控制模块可以接收无效请求并修改该位以指示事务请求的无效状态，并且当事务请求处于读取位置时丢弃事务请求。

    Direct memory access controller having programmable timing
    17.
    发明授权
    Direct memory access controller having programmable timing 失效
    具有可编程时序的直接存储器存取控制器

    公开(公告)号：US5884095A

    公开(公告)日：1999-03-16

    申请号：US815731

    申请日：1997-03-12

    申请人： Jeff W. Wolford ,  Robert Allan Lester

    发明人： Jeff W. Wolford ,  Robert Allan Lester

    IPC分类号： G06F13/28 ,  G06F13/30 ,  G06F13/362

    CPC分类号： G06F13/30 ,  G06F13/28 ,  G06F13/287 ,  G06F13/3625

    摘要： An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.

    摘要翻译： 改进的DMA控制器，具有可编程数据传输定时。 总循环时间不仅可编程，而且循环的有效和无效周期也可编程。 一个有效的定时寄存器和一个无效的定时寄存器与倒计时定时器结合使用，以确定数据传输周期的有效和无效周期。 有效时间段在有效阶段加载到定时器中，活动阶段的结束由定时器超时指示。 接下来，将非活动时间段加载到定时器中，其类似地超时以指示数据传送周期的非活动阶段的结束。

    System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system
    20.
    发明授权
    System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system 有权
    计算机系统中系统接口设备与总线接口设备之间的点对点串行通信的系统和方法

    公开(公告)号：US06363439B1

    公开(公告)日：2002-03-26

    申请号：US09206515

    申请日：1998-12-07

    申请人： John D. Battles ,  Paul B. Rawlins ,  Robert Allan Lester ,  Patrick L. Ferguson

    发明人： John D. Battles ,  Paul B. Rawlins ,  Robert Allan Lester ,  Patrick L. Ferguson

    IPC分类号： G06F1314

    CPC分类号： G06F13/4273 ,  G06F13/4004

    摘要： A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units. A pull-up device may be provided on the serial communication link to maintain a high voltage level on the link when it is not being driven by one of the bus interface units. The north bridge and south bridge may alternate between sending and receiving commands across the

    摘要翻译： 提供系统接口单元和外围总线接口单元之间的点对点串行通信链路。 系统总线接口单元可以在CPU总线和诸如PCI总线的外围总线之间进行接口，并且可以被称为北桥。 系统接口单元也可以连接到主存储器和高级图形端口。 外围总线接口单元可以在诸如PCI总线的第一外围总线和诸如ISA总线的第二外围总线之间进行接口，并且可以被称为南桥。 系统接口单元和总线接口单元之间的串行通信链路可以是使用来自第一外设总线的总线时钟作为定时参考的单线串行总线。 该时钟可能是PCI时钟。 串行通信链路可以使用系统接口单元上的单个引脚和总线接口单元上的单个引脚在接口单元之间传输命令。 可以在串行通信链路上提供上拉设备，以便当其不被总线接口单元中的一个驱动时，在链路上保持高电压电平。 北桥和南桥可以在发送和接收命令之间交替