公开(公告)号：US20220130610A1

公开(公告)日：2022-04-28

申请号：US17568868

申请日：2022-01-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU

IPC: H01G4/248 ,  H01G4/30 ,  H01G4/12 ,  H01G4/232 ,  H01G4/012

Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. A ratio of min to max is not less than about 36% and not more than about 90%, where A1, A2, A3, and A4 respectively denote the surface areas of first, second, third, and fourth external electrodes that are located on the first or second main surface of the stacked body.

公开(公告)号：US20200312565A1

公开(公告)日：2020-10-01

申请号：US16788427

申请日：2020-02-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Taisuke KANZAKI ,  Satoshi MURAMATSU ,  Kosuke ONISHI

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/12 ,  H01G4/012

Abstract: A multilayer ceramic capacitor includes a capacitive element including ceramic layers and internal electrodes, and external electrodes on the capacitive element. The external electrodes include a Ni underlying electrode layer mainly made of Ni, a Cu plating electrode layer, and at least one second plating electrode layer. The Cu plating electrode layer includes a Ni diffused Cu plating electrode layer on a side closer to the Ni underlying electrode layer and including Ni diffused therein and a non-Ni diffused Cu plating electrode layer on a side closer to the second plating electrode layer and not including Ni diffused therein. The Cu plating electrode layer has a thickness of about 3 μm or more and about 12 μm or less and the non-Ni diffused Cu plating electrode layer has a thickness of about 0.5 μm or more.

公开(公告)号：US20240258038A1

公开(公告)日：2024-08-01

申请号：US18626590

申请日：2024-04-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU

IPC: H01G4/248 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

CPC classification number: H01G4/248 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/1236 ,  H01G4/232 ,  H01G4/2325 ,  H01G4/30

Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. A ratio of min to max is not less than about 36% and not more than about 90%, where A1, A2, A3, and A4 respectively denote the surface areas of first, second, third, and fourth external electrodes that are located on the first or second main surface of the stacked body.

公开(公告)号：US20230307186A1

公开(公告)日：2023-09-28

申请号：US18122177

申请日：2023-03-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kosuke ONISHI ,  Satoshi MURAMATSU ,  Yukie WATANABE ,  Ryo NISHIMURA

IPC: H01G4/30 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G4/232

Abstract: A multilayer ceramic capacitor includes a ceramic body including ceramic layers, first internal electrodes, and second internal electrodes laminated in a height direction, a first external electrode on at least part of a first end surface and on part of a first main surface and not on a second main surface, the first external electrode being electrically connected to the first internal electrodes, a second external electrode on at least part of a second end surface and on part of the first main surface and is not on the second main surface, the second external electrode being electrically connected to the second internal electrodes, at least two penetration portions penetrating the ceramic body between the first and second main surfaces, and a reinforcing layer on at least part of the second main surface, the reinforcing layer covering the at least two penetration portions exposed from the ceramic body.

公开(公告)号：US20230253160A1

公开(公告)日：2023-08-10

申请号：US18125775

申请日：2023-03-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/012 ,  H01G4/232 ,  H01G4/008

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/012 ,  H01G4/232

Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. A ratio of min to max is not less than about 36% and not more than about 90%, where A1, A2, A3, and A4 respectively denote the surface areas of first, second, third, and fourth external electrodes that are located on the first or second main surface of the stacked body.

公开(公告)号：US20230230774A1

公开(公告)日：2023-07-20

申请号：US18127795

申请日：2023-03-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU

IPC: H01G4/30 ,  H01G2/02 ,  H01G4/012 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G2/02 ,  H01G4/012 ,  H01G4/1218

Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. The dielectric layers include outer layer portions and an effective layer portion. Each outer layer portion is adjacent to a corresponding main surface of the stacked body. Each outer layer portion is a dielectric layer located between a corresponding main surface and an internal electrode closest to the main surface. A ratio of a dimension of the effective layer portion in a stacking direction to a dimension of the stacked body in the stacking direction is not less than about 53% and not more than about 83%.

公开(公告)号：US20230095128A1

公开(公告)日：2023-03-30

申请号：US18075456

申请日：2022-12-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU ,  Ken TOMINAGA

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes an external electrode including an underlying electrode layer, a lower plating layer on the underlying electrode layer at a first end surface and a second end surface, and an upper plating layer on the lower plating layer. The underlying electrode layer is a thin film electrode including at least one selected from Ni, Cr, Cu, and Ti. The lower plating layer is a Cu plating layer including a lower layer region located closer to the multilayer body and an upper layer region located between the lower layer region and the upper plating layer, and the Cu plating layer in the lower layer region has a metal grain diameter smaller than that of the Cu plating layer located in the upper layer region.

公开(公告)号：US20210241976A1

公开(公告)日：2021-08-05

申请号：US17126263

申请日：2020-12-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Suguru NAKANO ,  Risa HOJO ,  Akira TANAKA ,  Toru NISHIKAWA ,  Satoshi MURAMATSU

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008 ,  H01G2/06

Abstract: A multilayer ceramic capacitor has a relationship of about 10°≤θ1≤about 50° and a relationship of about 10°≤θ2≤about 50°, where θ1 denotes an angle between a first end surface and a perpendicular extending from a side of a first main surface at a point of intersection of the first main surface and the first end surface, and θ2 denotes an angle between a second end surface and a perpendicular extending from a side of the first main surface at a point of intersection of the first main surface and the second end surface.

公开(公告)号：US20210183581A1

公开(公告)日：2021-06-17

申请号：US17119263

申请日：2020-12-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Suguru NAKANO ,  Satoshi MURAMATSU ,  Risa HOJO ,  Yoshiyuki NOMURA

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008 ,  H01G2/06

Abstract: A multilayer ceramic capacitor includes a laminate including dielectric layers and internal electrode layers, and external electrodes on surfaces of the laminate. A silane coupling agent layer is on at least a mounting surface among surfaces of the laminate. The silane coupling agent layer is made of a fluorine-based silane coupling agent, and a silane coupling agent concentration on the mounting surface is about 0.1 or higher and about 365 or lower and is higher than a silane coupling agent concentration on a counter surface opposing the mounting surface, or the silane coupling agent layer is made of a carbon-based silane coupling agent, and a silane coupling agent concentration on the mounting surface is about 0.91 or higher and about 38.10 or lower and is higher than a silane coupling agent concentration on a counter surface opposing the mounting surface.

公开(公告)号：US20200312564A1

公开(公告)日：2020-10-01

申请号：US16830314

申请日：2020-03-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kosuke ONISHI ,  Satoshi MURAMATSU ,  Taisuke KANZAKI

IPC: H01G4/232 ,  H01G4/012 ,  H01G4/30

Abstract: A multilayer ceramic capacitor includes a capacitive element including a stack of ceramic layers and internal electrodes, and external electrodes on a surface of the capacitive element. Each of the external electrodes includes a base electrode layer on the surface of the capacitive element and a Cu-plated electrode layer on a surface of the base electrode layer and including an edge portion facing the surface of the capacitive element. Sn is provided between the edge portion of the Cu-plated electrode layer and the surface of the capacitive element. On a surface of the Cu-plated electrode layer, at least one second plated electrode layer including an edge portion facing the surface of the capacitive element is provided.