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公开(公告)号：US20240153712A1
公开(公告)日：2024-05-09
申请号：US18410081
申请日：2024-01-11
发明人： Satoshi MURAMATSU , Ken TOMINAGA
摘要： A multilayer ceramic capacitor includes an external electrode including an underlying electrode layer, a lower plating layer on the underlying electrode layer at a first end surface and a second end surface, and an upper plating layer on the lower plating layer. The underlying electrode layer is a thin film electrode including at least one selected from Ni, Cr, Cu, and Ti. The lower plating layer is a Cu plating layer including a lower layer region located closer to the multilayer body and an upper layer region located between the lower layer region and the upper plating layer, and the Cu plating layer in the lower layer region has a metal grain diameter smaller than that of the Cu plating layer located in the upper layer region.
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公开(公告)号：US20230352242A1
公开(公告)日：2023-11-02
申请号：US18212809
申请日：2023-06-22
发明人： Suguru NAKANO , Satoshi MURAMATSU , Risa HOJO , Yoshiyuki NOMURA
CPC分类号： H01G4/30 , H01G4/012 , H01G2/065 , H01G4/008 , H01G4/1218
摘要： A multilayer ceramic capacitor includes a laminate including dielectric layers and internal electrode layers, and first and second external electrodes on surfaces of the laminate. The laminate includes first and second main surfaces oppose each other in a lamination direction, first and second side surfaces oppose each other in a length direction perpendicular or substantially perpendicular to the lamination direction, and third and fourth side surfaces oppose each other in a width direction perpendicular or substantially perpendicular to the lamination direction and the length direction. A length ratio EB1/EA1 of the first external electrode wrapping around to main surfaces of the laminate is about 0 or more and about 0.5 or less. A length ratio EB2/EA2 of the second external electrode wrapping around to the main surfaces of the laminate is about 0 or more and about 0.5 or less.
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公开(公告)号：US20230298818A1
公开(公告)日：2023-09-21
申请号：US18105301
申请日：2023-02-03
发明人： Kotaro KISHI , Satoshi MURAMATSU
摘要： A multilayer ceramic capacitor includes a multilayer body in which a dimension in a width direction >a dimension in a length direction >a dimension in a height direction is satisfied. A dimension in the length direction of each of lateral surface exposed portions is about 10% or more and about 44% or less with respect to the dimension in the length direction. A dimension of the external electrode in the length direction is about 17% or more and about 48% or less with respect to the dimension in the length direction.
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公开(公告)号：US20220208459A1
公开(公告)日：2022-06-30
申请号：US17532268
申请日：2021-11-22
发明人： Satoshi MURAMATSU
摘要： A multilayer ceramic capacitor includes a multilayer body including layered ceramic layers and internal electrode layers, and an external electrode on a side surface of the multilayer body and connected to the internal electrode layers. A recess is provided in a surface of the external electrode on one side of opposing main surfaces of the multilayer ceramic capacitor.
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公开(公告)号：US20220130610A1
公开(公告)日：2022-04-28
申请号：US17568868
申请日：2022-01-05
发明人： Satoshi MURAMATSU
摘要： A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. A ratio of min to max is not less than about 36% and not more than about 90%, where A1, A2, A3, and A4 respectively denote the surface areas of first, second, third, and fourth external electrodes that are located on the first or second main surface of the stacked body.
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16.发明申请公开(公告)号：US20200312565A1
公开(公告)日：2020-10-01
申请号：US16788427
申请日：2020-02-12
摘要： A multilayer ceramic capacitor includes a capacitive element including ceramic layers and internal electrodes, and external electrodes on the capacitive element. The external electrodes include a Ni underlying electrode layer mainly made of Ni, a Cu plating electrode layer, and at least one second plating electrode layer. The Cu plating electrode layer includes a Ni diffused Cu plating electrode layer on a side closer to the Ni underlying electrode layer and including Ni diffused therein and a non-Ni diffused Cu plating electrode layer on a side closer to the second plating electrode layer and not including Ni diffused therein. The Cu plating electrode layer has a thickness of about 3 μm or more and about 12 μm or less and the non-Ni diffused Cu plating electrode layer has a thickness of about 0.5 μm or more.
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公开(公告)号：US20240258038A1
公开(公告)日：2024-08-01
申请号：US18626590
申请日：2024-04-04
发明人： Satoshi MURAMATSU
CPC分类号： H01G4/248 , H01G4/008 , H01G4/012 , H01G4/12 , H01G4/1227 , H01G4/1236 , H01G4/232 , H01G4/2325 , H01G4/30
摘要： A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. A ratio of min to max is not less than about 36% and not more than about 90%, where A1, A2, A3, and A4 respectively denote the surface areas of first, second, third, and fourth external electrodes that are located on the first or second main surface of the stacked body.
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公开(公告)号：US20230307186A1
公开(公告)日：2023-09-28
申请号：US18122177
申请日：2023-03-16
摘要： A multilayer ceramic capacitor includes a ceramic body including ceramic layers, first internal electrodes, and second internal electrodes laminated in a height direction, a first external electrode on at least part of a first end surface and on part of a first main surface and not on a second main surface, the first external electrode being electrically connected to the first internal electrodes, a second external electrode on at least part of a second end surface and on part of the first main surface and is not on the second main surface, the second external electrode being electrically connected to the second internal electrodes, at least two penetration portions penetrating the ceramic body between the first and second main surfaces, and a reinforcing layer on at least part of the second main surface, the reinforcing layer covering the at least two penetration portions exposed from the ceramic body.
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公开(公告)号：US20230253160A1
公开(公告)日：2023-08-10
申请号：US18125775
申请日：2023-03-24
发明人： Satoshi MURAMATSU
摘要： A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. A ratio of min to max is not less than about 36% and not more than about 90%, where A1, A2, A3, and A4 respectively denote the surface areas of first, second, third, and fourth external electrodes that are located on the first or second main surface of the stacked body.
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公开(公告)号：US20230230774A1
公开(公告)日：2023-07-20
申请号：US18127795
申请日：2023-03-29
发明人： Satoshi MURAMATSU
CPC分类号： H01G4/30 , H01G2/02 , H01G4/012 , H01G4/1218
摘要： A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. The dielectric layers include outer layer portions and an effective layer portion. Each outer layer portion is adjacent to a corresponding main surface of the stacked body. Each outer layer portion is a dielectric layer located between a corresponding main surface and an internal electrode closest to the main surface. A ratio of a dimension of the effective layer portion in a stacking direction to a dimension of the stacked body in the stacking direction is not less than about 53% and not more than about 83%.
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