-
公开(公告)号：US20210383749A1
公开(公告)日：2021-12-09
申请号：US17409824
申请日：2021-08-24
Applicant: Novatek Microelectronics Corp.
Inventor： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Po-Hsiang Fang , Ju-Lin Huang
IPC: G09G3/32
Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.
-
公开(公告)号：US11010136B2
公开(公告)日：2021-05-18
申请号：US16159734
申请日：2018-10-15
Applicant: Novatek Microelectronics Corp.
Inventor： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang
Abstract: A random bit stream generator which includes a pseudo-random bit stream generator and a multi-stage noise shaping (MASH) delta-sigma modulator is introduced. The pseudo-random bit stream generator may generate a first random bit stream according to a first clock signal. The MASH delta-sigma modulator is coupled to the first random bit stream generator to receive the first random bit stream and output a second random bit stream according to the first random bit stream and a second clock signal. A frequency of the second clock signal is greater than a frequency of the first clock signal, and the random bit stream has bell-shaped distribution. A method of generating a random bit stream having bell-shaped distribution adapted to a random bit stream generator is also introduced.
-
公开(公告)号：US20210049956A1
公开(公告)日：2021-02-18
申请号：US17004025
申请日：2020-08-27
Applicant: Novatek Microelectronics Corp.
Inventor： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Po-Hsiang Fang , Ju-Lin Huang
IPC: G09G3/32
Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.
-
公开(公告)号：US20180198597A1
公开(公告)日：2018-07-12
申请号：US15863983
申请日：2018-01-08
Applicant: Novatek Microelectronics Corp.
Inventor： Chang-Cheng Huang , Shen-Iuan Liu , Ju-Lin Huang , Tzu-Chien Tzeng , Keko-Chun Liang , Yu-Hsiang Wang , Che-Wei Yeh
CPC classification number: H04L7/0016 , H03L7/0807 , H03L7/087 , H03L7/0891 , H03L7/0898 , H03L7/091 , H03L7/093 , H03L2207/06
Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.
-
公开(公告)号：US12142245B2
公开(公告)日：2024-11-12
申请号：US17945082
申请日：2022-09-14
Applicant: NOVATEK Microelectronics Corp.
Inventor： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yong-Ren Fang , Yi-Chuan Liu , Yi-Yang Tsai , Po-Hsiang Fang
Abstract: A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.
-
Patent Agency Ranking
公开(公告)号：US12142190B1
公开(公告)日：2024-11-12
申请号：US18522263
申请日：2023-11-29
Applicant: NOVATEK Microelectronics Corp.
Inventor： Chieh-An Lin , Chun-Wei Kang , Po-Hsiang Fang , Keko-Chun Liang , Jhih-Siou Cheng , Nien-Tsung Hsueh , Che-Wei Yeh , Yu-Hsiang Wang
Abstract: A display control system for controlling a display panel having a plurality of display zones includes a main controller, a plurality of display driver circuits and a plurality of memories. Each of the display driver circuits is coupled to a corresponding display zone among the plurality of display zones, to control the corresponding display zone. Each of the memories is coupled to a corresponding display driver circuit among the plurality of display driver circuits, to store a compensation data for the corresponding display zone controlled by the corresponding display driver circuit. The plurality of display driver circuits are cascaded through a plurality of first transmission channels and connected through at least one second transmission channel, and each of the first transmission channels is coupled between two of the plurality of display driver circuits or between one of the plurality of display driver circuits and the main controller.
-
公开(公告)号：US11749168B1
公开(公告)日：2023-09-05
申请号：US17857154
申请日：2022-07-04
Applicant: Novatek Microelectronics Corp.
Inventor： Ho-Chun Chang , Che-Wei Yeh , Yu-Hsiang Wang , Keko-Chun Liang
IPC: G09G3/20
CPC classification number: G09G3/2092 , G09G2300/0838 , G09G2310/0289
Abstract: The disclosure provides a data receiver, including a first capacitor, a second capacitor, a first inverter and a second inverter. The first capacitor has a first terminal and a second terminal, and the first terminal receives a first input signal. The second capacitor has a third terminal and a fourth terminal, and the third terminal receives a second input signal. The first inverter has a first input terminal and a first output terminal. The second inverter has a second input terminal and a second output terminal. The first input terminal and the second output terminal are coupled to the second terminal of the first capacitor, and the second input terminal and the first output terminal are coupled to the fourth terminal of the second capacitor. The first output terminal generates a first output signal with a first output voltage, and the second output terminal generates a second output signal with a second output voltage.
-
公开(公告)号：US11527195B2
公开(公告)日：2022-12-13
申请号：US17238179
申请日：2021-04-22
Applicant: NOVATEK Microelectronics Corp.
Inventor： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yong-Ren Fang , Yi-Chuan Liu
Abstract: A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.
-
公开(公告)号：US20220254305A1
公开(公告)日：2022-08-11
申请号：US17721337
申请日：2022-04-14
Applicant: Novatek Microelectronics Corp.
Inventor： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yong-Ren Fang , Yi-Chuan Liu
IPC: G09G3/32
Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N−1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N−1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.
-
公开(公告)号：US11341904B2
公开(公告)日：2022-05-24
申请号：US17138772
申请日：2020-12-30
Applicant: Novatek Microelectronics Corp.
Inventor： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yong-Ren Fang , Yi-Chuan Liu
IPC: G09G3/32
Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N−1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N−1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.
-
-
-
-
-
-
-
-
-
Search Results
32
records
(took 0.015 seconds)
