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    METHOD OF TRANSPORTING DATA WITH EMBEDDED CLOCK
    11.
    发明申请
    METHOD OF TRANSPORTING DATA WITH EMBEDDED CLOCK 审中-公开
    用嵌入式时钟传输数据的方法

    公开(公告)号：US20160050090A1

    公开(公告)日：2016-02-18

    申请号：US14925988

    申请日：2015-10-29

    Applicant: Novatek Microelectronics Corp.

    Inventor： Chia-Wei Su ,  Chu-Ya Hsiao

    IPC: H04L25/49 ,  H04L12/741

    CPC classification number: H04L25/4908 ,  H04L25/0272 ,  H04L45/74

    Abstract: A method for transporting data to a display device includes: receiving image data having a first part data and a second part data; determining a coding information of a header according to a bit number of the image data with consecutively same bit value, wherein the coding information indicates whether the second part data in bits is to be inverted or not; coding the image data according to the coding information; and packing the header and the coded image data to a packet for transporting to the display device.

    Abstract translation: 一种将数据传送到显示设备的方法包括：接收具有第一部分数据和第二部分数据的图像数据; 根据具有连续相同比特值的图像数据的比特数，确定头部的编码信息，其中编码信息指示比特中的第二部分数据是否被反转; 根据编码信息对图像数据进行编码; 并将标题和编码图像数据打包到用于传送到显示装置的分组。

    SOURCE DRIVER AND METHOD FOR DRIVING DISPLAY DEVICE
    12.
    发明申请
    SOURCE DRIVER AND METHOD FOR DRIVING DISPLAY DEVICE 审中-公开
    用于驱动显示设备的源驱动器和方法

    公开(公告)号：US20150084947A1

    公开(公告)日：2015-03-26

    申请号：US14561200

    申请日：2014-12-04

    Applicant: Novatek Microelectronics Corp.

    Inventor： Jr-Ching Lin ,  Hsin-Hung Lee ,  Chia-Wei Su ,  Po-Yu Tseng ,  Shun-Hsun Yang ,  Po-Hsiang Fang

    IPC: G09G3/36

    CPC classification number: G09G3/3696 ,  G09G1/005 ,  G09G3/3688 ,  G09G2320/0673

    Abstract: A source driver includes a first drive channel circuit, a voltage controller and a first programmable voltage buffer unit. The first drive channel circuit receives a first pixel data and a first reference voltage group, for driving the display device. The voltage controller receives a voltage command during a line data transmitting period, a horizontal blanking period or a vertical blanking period for generating a first reference voltage configuration data. The first programmable voltage buffer unit is coupled to the voltage controller and the first drive channel circuit, and receives the first reference voltage configuration data for applying the first reference voltage group to the first drive channel circuit. Furthermore, a method for driving a display device is also provided.

    Abstract translation: 源驱动器包括第一驱动通道电路，电压控制器和第一可编程电压缓冲器单元。 第一驱动通道电路接收第一像素数据和第一参考电压组，用于驱动显示装置。 电压控制器在行数据发送期间，水平消隐期间或垂直消隐期间接收电压指令，以产生第一参考电压配置数据。 第一可编程电压缓冲器单元耦合到电压控制器和第一驱动通道电路，并且接收用于将第一参考电压组施加到第一驱动通道电路的第一参考电压配置数据。 此外，还提供了一种用于驱动显示装置的方法。

    Timing controller, source driver, display driving circuit, and display driving method
    13.
    发明授权
    Timing controller, source driver, display driving circuit, and display driving method 有权
    定时控制器，源驱动器，显示驱动电路和显示驱动方式

    公开(公告)号：US08922535B2

    公开(公告)日：2014-12-30

    申请号：US13845080

    申请日：2013-03-17

    Applicant: Novatek Microelectronics Corp.

    Inventor： Shun-Hsun Yang ,  Chia-Wei Su

    IPC: G09G5/00

    CPC classification number: G09G5/00 ,  G09G3/20 ,  G09G5/18 ,  G09G2330/06 ,  G09G2370/08

    Abstract: A timing controller is provided. The timing controller includes a timing control circuit, a first scrambler and a second scrambler. The timing control circuit provides first source driving data and second source driving data. The first scrambler scrambles the first source driving data according to a first random number to generate first scrambled data. The second scrambler scrambles the second driving source data according to a second random number to generate second scrambled data. The second random number is different from the first random number.

    Abstract translation: 提供了时序控制器。 定时控制器包括定时控制电路，第一扰频器和第二加扰器。 定时控制电路提供第一源驱动数据和第二源驱动数据。 第一加扰器根据第一随机数对第一源驱动数据进行加扰，以产生第一加扰数据。 第二加扰器根据第二随机数对第二驱动源数据进行加扰，以产生第二加扰数据。 第二个随机数与第一个随机数不同。

    TIMING CONTROLLER, SOURCE DRIVER, DISPLAY DRIVING CIRCUIT, AND DISPLAY DRIVING METHOD
    14.
    发明申请
    TIMING CONTROLLER, SOURCE DRIVER, DISPLAY DRIVING CIRCUIT, AND DISPLAY DRIVING METHOD 有权
    时序控制器，源驱动器，显示驱动电路和显示驱动方法

    公开(公告)号：US20140132575A1

    公开(公告)日：2014-05-15

    申请号：US13845080

    申请日：2013-03-17

    Applicant: NOVATEK MICROELECTRONICS CORP.

    Inventor： Shun-Hsun YANG ,  Chia-Wei Su

    IPC: G09G5/00

    CPC classification number: G09G5/00 ,  G09G3/20 ,  G09G5/18 ,  G09G2330/06 ,  G09G2370/08

    Abstract: A timing controller is provided. The timing controller includes a timing control circuit, a first scrambler and a second scrambler. The timing control circuit provides first source driving data and second source driving data. The first scrambler scrambles the first source driving data according to a first random number to generate first scrambled data. The second scrambler scrambles the second driving source data according to a second random number to generate second scrambled data. The second random number is different from the first random number.

    Abstract translation: 提供了时序控制器。 定时控制器包括定时控制电路，第一扰频器和第二加扰器。 定时控制电路提供第一源驱动数据和第二源驱动数据。 第一加扰器根据第一随机数对第一源驱动数据进行加扰，以产生第一加扰数据。 第二加扰器根据第二随机数对第二驱动源数据进行加扰，以产生第二加扰数据。 第二个随机数与第一个随机数不同。

    METHOD FOR DISPLAYING ERROR RATES OF DATA CHANNELS OF DISPLAY
    15.
    发明申请
    METHOD FOR DISPLAYING ERROR RATES OF DATA CHANNELS OF DISPLAY 有权
    显示数据通道错误率的方法

    公开(公告)号：US20140049524A1

    公开(公告)日：2014-02-20

    申请号：US13778122

    申请日：2013-02-27

    Applicant: NOVATEK MICROELECTRONICS CORP.

    Inventor： Shun-Hsun Yang ,  Chia-Wei Su ,  Po-Yu Tseng ,  Po-Hsiang Fang ,  Hsin-Hung Lee

    IPC: G09G3/00

    CPC classification number: G09G3/006 ,  G09G3/3688 ,  G09G2330/12 ,  G09G2370/08

    Abstract: A method for displaying error rates of data channels of a display is provided. A timing controller of the display repeatedly transmits a test signal with a specific format to a first and a second source drivers of the display via a first and a second data channels of the display. During testing, a first number and a second number of times of the first source driver and the second source driver determining that the received test signal does not have the specific format are counted respectively. The first and the second source drivers control displaying of a first area and a second area of a panel of the display respectively according to the counted first and second numbers of times. Accordingly, the error rates of the data channels are presented on the panel of the display in a way that the error rates could be recognized more easily.

    Abstract translation: 提供了一种用于显示显示器的数据通道的错误率的方法。 显示器的定时控制器经由显示器的第一和第二数据通道重复地将特定格式的测试信号发送到显示器的第一和第二源驱动器。 在测试期间，分别计数第一源驱动器和第二源驱动器的第一次数和第二次数，以确定所接收的测试信号不具有特定格式。 第一和第二源驱动器分别根据计数的第一和第二次数来分别显示显示器的面板的第一区域和第二区域。 因此，数据通道的错误率以更容易识别错误率的方式呈现在显示器的面板上。

    Flat Panel Display with Multi-Drop Interface
    16.
    发明申请
    Flat Panel Display with Multi-Drop Interface 审中-公开
    带多点接口的平板显示器

    公开(公告)号：US20140009450A1

    公开(公告)日：2014-01-09

    申请号：US13935546

    申请日：2013-07-04

    Applicant: NOVATEK Microelectronics Corp.

    Inventor： Chia-Wei Su ,  Shun-Hsun Yang ,  Hsin-Hung Lee ,  Po-Hsiang Fang ,  Po-Yu Tseng ,  Li-Tang Lin

    IPC: G09G5/00

    CPC classification number: G09G5/001 ,  G09G3/20 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0281 ,  G09G2310/0297

    Abstract: A flat panel display with multi-drop interfaces is disclosed. The flat panel display with multi-drop interfaces includes a plurality of driver chips having a plurality of respective hardware setting values via a hardware setting, and a timing controller for transmitting at least one signal to the plurality of driver chips via at least one multi-drop interface, wherein the timing controller and a specific driver chip among the plurality of driver chips negotiate with each other according to a corresponding specific respective hardware setting value among the plurality of respective hardware setting values.

    Abstract translation: 公开了具有多点接口的平板显示器。 具有多点接口的平板显示器包括经由硬件设置具有多个相应的硬件设置值的多个驱动器芯片，以及定时控制器，用于经由至少一个多点接口将至少一个信号发送到多个驱动器芯片， 其中所述定时控制器和所述多个驱动器芯片中的特定驱动器芯片根据所述多个相应硬件设置值中的对应的特定相应的硬件设置值来彼此协商。

    Amplifier circuit with overshoot suppression
    17.
    发明授权
    Amplifier circuit with overshoot suppression 有权

    公开(公告)号：US11290061B2

    公开(公告)日：2022-03-29

    申请号：US16929124

    申请日：2020-07-15

    Applicant: Novatek Microelectronics Corp.

    Inventor： Chia-Wei Su ,  Ju-Lin Huang ,  Keko-Chun Liang

    IPC: H03F1/08 ,  H03F1/52 ,  H03F3/30 ,  H03F3/45

    Abstract: An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier includes a PMOSFET and an NMOSFET. The PMOSFET has a gate electrode serving as a first input end and a drain coupled to an output end. The NMOSFET has a gate electrode serving as a second input end and a drain coupled to the output end. The output amplifier outputs an output voltage at the output end, and is coupled to the input amplifier via at least one of the first and second input ends. The diode device is coupled between the output end and the at least one of the first and second input ends of the output amplifier. When a voltage difference between the output end and the at least one of the first and second input ends of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.

    Method of transporting data with embedded clock
    20.
    发明授权
    Method of transporting data with embedded clock 有权

    公开(公告)号：US09860090B2

    公开(公告)日：2018-01-02

    申请号：US14925988

    申请日：2015-10-29

    Applicant: Novatek Microelectronics Corp.

    Inventor： Chia-Wei Su ,  Chu-Ya Hsiao

    IPC: H04L25/49 ,  H04L25/02 ,  H04L12/741

    CPC classification number: H04L25/4908 ,  H04L25/0272 ,  H04L45/74

    Abstract: A method for transporting data to a display device includes: receiving image data having a first part data and a second part data; determining a coding information of a header according to a bit number of the image data with consecutively same bit value, wherein the coding information indicates whether the second part data in bits is to be inverted or not; coding the image data according to the coding information; and packing the header and the coded image data to a packet for transporting to the display device.

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