公开(公告)号：US11810632B2

公开(公告)日：2023-11-07

申请号：US17892336

申请日：2022-08-22

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jue Wu

IPC: G11C29/00 ,  G11C29/32 ,  G06F9/30 ,  G11C29/16

CPC classification number: G11C29/32 ,  G06F9/30101 ,  G06F9/30134 ,  G11C29/16

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.

公开(公告)号：US20220399069A1

公开(公告)日：2022-12-15

申请号：US17892336

申请日：2022-08-22

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jue Wu

IPC: G11C29/32 ,  G06F9/30 ,  G11C29/16

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.

公开(公告)号：US20220365857A1

公开(公告)日：2022-11-17

申请号：US17320025

申请日：2021-05-13

Applicant: NVIDIA Corporation

Inventor： Sailendra Chadalavada ,  Anitha Kalva ,  Abilash Nerallapally ,  Milind Sonawane ,  Shantanu Sarangi ,  Ashok Aravamudhan ,  Sridharan Ramakrishnan ,  Sam Edirisooriya ,  Hari Krishnan

IPC: G06F11/263 ,  G06F11/27 ,  G06F11/273 ,  G06F11/14

Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.

公开(公告)号：US11079434B2

公开(公告)日：2021-08-03

申请号：US16598558

申请日：2019-10-10

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jue Wu

IPC: G01R31/3187 ,  G01R31/3177 ,  G06F13/16 ,  G06Q10/08 ,  G11C29/16 ,  G01R31/319 ,  G11C29/26

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

公开(公告)号：US20200075116A1

公开(公告)日：2020-03-05

申请号：US16557615

申请日：2019-08-30

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jue Wu

IPC: G11C29/32 ,  G11C29/16 ,  G06F9/30

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.