公开(公告)号：US20160225758A1

公开(公告)日：2016-08-04

申请号：US15013070

申请日：2016-02-02

Applicant: NXP B.V.

Inventor： Da-Wei Lai ,  Dolphin Abessolo Bidzo

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/092

CPC classification number: H01L27/0292 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/092 ,  H02H9/046

Abstract: A semiconductor device and method. The device includes a first domain and a second domain each having a power rail and a ground rail. The device further includes a signal line connected between the first domain and the second domain. The device also includes an electrostatic discharge protection circuit for providing cross-domain ESD protection. The protection circuit includes a blocking transistor connected between the first domain power rail and the signal line. The protection circuit also includes a power rail clamp connected between the first domain power rail and the first domain ground rail. The power rail clamp is operable to apply a control signal to a gate of the blocking transistor to switch it on during normal operation and to switch it off during an ESD event. The power rail clamp is operable during the ESD event to conduct an ESD current.

Abstract translation: 半导体器件和方法。 该装置包括第一域和第二域，每个具有电力轨和地轨。 该装置还包括连接在第一域和第二域之间的信号线。 该器件还包括用于提供跨域ESD保护的静电放电保护电路。 保护电路包括连接在第一域电源轨和信号线之间的阻塞晶体管。 保护电路还包括连接在第一域电源轨和第一域接地轨之间的电力轨夹。 电源轨钳位可操作以将控制信号施加到阻塞晶体管的栅极，以在正常操作期间将其接通，并在ESD事件期间将其切断。 电源轨钳位在ESD事件期间可操作以传导ESD电流。

公开(公告)号：US12206237B2

公开(公告)日：2025-01-21

申请号：US17938151

申请日：2022-10-05

Applicant: NXP B.V.

Inventor： Dolphin Abessolo Bidzo ,  Shailesh Kulkarni ,  Juan Felipe Osorio Tamayo

IPC: H02H9/04 ,  H01F27/28

Abstract: A semiconductor die includes a transformer with terminals of a first winding electrically coupled to external die terminals of the semiconductor die. The terminals of a second winding of the transformer are coupled to internal circuitry of the semiconductor die. An ESD clamp circuit is electrically coupled to the center tap of the second winding of the transformer. When made conductive during and ESD event, the ESD clamp circuit discharges ESD current between the center tap and a supply rail.

公开(公告)号：US20240120734A1

公开(公告)日：2024-04-11

申请号：US17938151

申请日：2022-10-05

Applicant: NXP B.V.

Inventor： Dolphin Abessolo Bidzo ,  Shailesh Kulkarni ,  Juan Felipe Osorio Tamayo

IPC: H02H9/04 ,  H01F27/28

CPC classification number: H02H9/046 ,  H01F27/28

Abstract: A semiconductor die includes a transformer with terminals of a first winding electrically coupled to external die terminals of the semiconductor die. The terminals of a second winding of the transformer are coupled to internal circuitry of the semiconductor die. An ESD clamp circuit is electrically coupled to the center tap of the second winding of the transformer. When made conductive during and ESD event, the ESD clamp circuit discharges ESD current between the center tap and a supply rail.

公开(公告)号：US20240113100A1

公开(公告)日：2024-04-04

申请号：US17936475

申请日：2022-09-29

Applicant: NXP B.V.

Inventor： Dolphin Abessolo Bidzo

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0259 ,  H01L27/0288 ,  H02H9/046 ,  H01L27/0255

Abstract: A semiconductor die has ESD clamp circuits that include vertical PNP transistors. The vertical PNP transistors include at least one region in a semiconductor substrate that is substrate isolated from a biased portion of the substrate. The ESD clamp circuits include a resistive element that is electrically coupled in a conductive path between the emitter and base of the vertical PNP transistor. The PNP transistor is conductive during certain ESD events to discharge ESD charge from the emitter to the collector.

公开(公告)号：US10784257B2

公开(公告)日：2020-09-22

申请号：US16120098

申请日：2018-08-31

Applicant: NXP B.V.

Inventor： Petrus Hubertus Cornelis Magnee ,  Pieter Simon van Dijk ,  Johannes Josephus Theodorus Marinus Donkers ,  Dolphin Abessolo Bidzo

IPC: H01L27/082 ,  H01L21/02 ,  H01L21/225 ,  H01L21/266 ,  H01L21/306 ,  H01L21/324 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737

Abstract: This specification discloses methods for integrating a SiGe-based HBT (heterojunction bipolar transistor) and a Si-based BJT (bipolar junction transistor) together in a single manufacturing process that does not add a lot of process complexity, and an integrated circuit that can be fabricated utilizing such a streamlined manufacturing process. In some embodiments, such an integrated circuit can enjoy both the benefits of a higher RF (radio frequency) performance for the SiGe HBT and a lower leakage current for the Si-based BJT. In some embodiments, such an integrated circuit can be applied to an ESD (electrostatic discharge) clamp circuit, in order to achieve a lower, or no, yield-loss.

公开(公告)号：US10074647B2

公开(公告)日：2018-09-11

申请号：US15013070

申请日：2016-02-02

Applicant: NXP B.V.

Inventor： Da-Wei Lai ,  Dolphin Abessolo Bidzo

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/092

CPC classification number: H01L27/0292 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/092 ,  H02H9/046

Abstract: A semiconductor device and method. The device includes a first domain and a second domain each having a power rail and a ground rail. The device further includes a signal line connected between the first domain and the second domain. The device also includes an electrostatic discharge protection circuit for providing cross-domain ESD protection. The protection circuit includes a blocking transistor connected between the first domain power rail and the signal line. The protection circuit also includes a power rail clamp connected between the first domain power rail and the first domain ground rail. The power rail clamp is operable to apply a control signal to a gate of the blocking transistor to switch it on during normal operation and to switch it off during an ESD event. The power rail clamp is operable during the ESD event to conduct an ESD current.