公开(公告)号：US12159845B2

公开(公告)日：2024-12-03

申请号：US17673636

申请日：2022-02-16

Applicant: NXP USA, Inc.

Inventor： Humayun Kabir ,  Vikas Shilimkar ,  Ibrahim Khalil ,  Kevin Kim

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/48 ,  H01L23/66 ,  H01L29/06

Abstract: A device includes a semiconductor substrate, a source metallization over an active area of the semiconductor substrate, a through-substrate via electrically connected to the source metallization, and an input bond pad formed in the semiconductor substrate and spaced apart from the active area. The input bond pad is electrically connected to a set of gate structures. The device includes a first inductive coil over the semiconductor substrate between a first portion of the source metallization and a second portion of the source metallization and a first capacitor over the semiconductor substrate between the first portion of the source metallization and the second portion of the source metallization. The first inductive coil and the first capacitor are connected in series between the input bond pad and the through-substrate via.

公开(公告)号：US12119300B2

公开(公告)日：2024-10-15

申请号：US17663181

申请日：2022-05-12

Applicant: NXP USA, Inc.

Inventor： Humayun Kabir ,  Ibrahim Khalil ,  Daniel Joseph Lamey ,  Yu-Ting David Wu

IPC: H01L25/10 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H03K17/687

CPC classification number: H01L23/528 ,  H01L21/823475 ,  H01L25/105 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41725 ,  H03K17/6871

Abstract: A device having a reference transistor fabricated within the same semiconductor substrate as a primary transistor (e.g., configured for use in a radiofrequency amplifier or other active circuit) has a shared metallization area coupled to a current terminal of both transistors configured to shield a control terminal of the reference transistor from coupling of alternating current interference from alternating currents within the primary transistor.

公开(公告)号：US11387169B2

公开(公告)日：2022-07-12

申请号：US16984286

申请日：2020-08-04

Applicant: NXP USA, Inc.

Inventor： Ibrahim Khalil ,  Kevin Kim ,  Humayun Kabir

IPC: H01L23/482 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor device includes an active region formed in a substrate. The active region includes input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. An input port is electrically connected to the input fingers and an output port is electrically connected to the output fingers. A common region is electrically connected to the common fingers. At least one of the input and output ports is positioned within the active region between the input, output, and common fingers. The common region is interposed between a pair of the common fingers such that the common fingers of the pair are spaced apart by a gap, and at least one of the input and output ports is position in the gap.

公开(公告)号：US20200098683A1

公开(公告)日：2020-03-26

申请号：US16142713

申请日：2018-09-26

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Hernan Rueda ,  Humayun Kabir

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/8234 ,  H01L21/56 ,  H01L27/088

Abstract: A transistor includes a semiconductor substrate having an active device region formed therein and an interconnect structure on a first surface of the semiconductor substrate. The interconnect structure is formed of multiple layers of dielectric material and electrically conductive material. Drain and gate runners are formed in the interconnect structure. A shield structure extends above a second surface of the interconnect structure, the shield structure being positioned between the drain and gate runners.

公开(公告)号：US12237257B2

公开(公告)日：2025-02-25

申请号：US17448709

申请日：2021-09-24

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Charles John Lessard ,  Humayun Kabir

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/528

Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.

公开(公告)号：US20230411243A1

公开(公告)日：2023-12-21

申请号：US17807841

申请日：2022-06-20

Applicant: NXP USA, Inc.

Inventor： Humayun Kabir ,  Ibrahim Khalil ,  Bruce McRae Green

IPC: H01L23/48 ,  H01L29/417

CPC classification number: H01L23/481 ,  H01L29/4175

Abstract: A transistor die includes input and output terminals and a source through-substrate via (TSV) between the input and output terminals. First and second primary drain contacts extend from the output terminal toward the input terminal past first and second sides, respectively, of the source TSV. An ancillary region is located adjacent to the source TSV, and boundaries of the ancillary region are defined by the source TSV, the first and second drain contacts, and one of the input terminal or the output terminal. The transistor further includes a primary transistor element, including a primary drain contact, a primary source contact, and a primary gate structure, located outside of the first ancillary region, and an ancillary transistor element, including an ancillary drain contact, an ancillary source contact, and an ancillary gate structure, located within the ancillary region.

公开(公告)号：US11430874B2

公开(公告)日：2022-08-30

申请号：US17123939

申请日：2020-12-16

Applicant: NXP USA, INC.

Inventor： Humayun Kabir ,  Ibrahim Khalil

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L23/66

Abstract: A semiconductor device includes a semiconductor substrate, a first current-carrying electrode, a second current-carrying electrode, a first control electrode disposed between the first current-carrying electrode and the second current-carrying electrode, a third current-carrying electrode electrically coupled to the first current-carrying electrode, and a fourth current-carrying electrode adjacent the third current-carrying electrode. The third current-carrying electrode and the fourth current-carrying electrode are configured to support current flow from the third current-carrying electrode to the fourth current-carrying electrode parallel to a second direction. The fourth current-carrying element is electrically coupled to the second current-carrying electrode and a second control electrode. The second control electrode is electrically coupled to the first control electrode. A first crossing region is electrically coupled to the first control electrode and a second crossing region is electrically coupled to the fourth current-carrying electrode, wherein the second crossing region crosses a portion of the first crossing region.

公开(公告)号：US20220190126A1

公开(公告)日：2022-06-16

申请号：US17123939

申请日：2020-12-16

Applicant: NXP USA, INC.

Inventor： Humayun Kabir ,  Ibrahim Khalil

IPC: H01L29/417 ,  H01L23/66 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, a first current-carrying electrode, a second current-carrying electrode, a first control electrode disposed between the first current-carrying electrode and the second current-carrying electrode, a third current-carrying electrode electrically coupled to the first current-carrying electrode, and a fourth current-carrying electrode adjacent the third current-carrying electrode. The third current-carrying electrode and the fourth current-carrying electrode are configured to support current flow from the third current-carrying electrode to the fourth current-carrying electrode parallel to a second direction. The fourth current-carrying element is electrically coupled to the second current-carrying electrode and a second control electrode. The second control electrode is electrically coupled to the first control electrode. A first crossing region is electrically coupled to the first control electrode and a second crossing region is electrically coupled to the fourth current-carrying electrode, wherein the second crossing region crosses a portion of the first crossing region.

公开(公告)号：US20220013451A1

公开(公告)日：2022-01-13

申请号：US17448709

申请日：2021-09-24

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Charles John Lessard ,  Humayun Kabir

IPC: H01L23/522 ,  H01L23/528

Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.

公开(公告)号：US11177207B2

公开(公告)日：2021-11-16

申请号：US16720579

申请日：2019-12-19

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Charles John Lessard ,  Humayun Kabir

IPC: H01L23/522 ,  H01L23/528

Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.