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    Data acknowledgment using impedance mismatching
    12.
    发明申请
    Data acknowledgment using impedance mismatching 失效
    使用阻抗失配的数据确认

    公开(公告)号：US20050076170A1

    公开(公告)日：2005-04-07

    申请号：US10680756

    申请日：2003-10-07

    申请人： Michael Boudreaux ,  Adam Courchesne ,  Jason Norman ,  Mark Styduhar ,  Sebastian Ventrone

    发明人： Michael Boudreaux ,  Adam Courchesne ,  Jason Norman ,  Mark Styduhar ,  Sebastian Ventrone

    IPC分类号： G06F12/00

    CPC分类号： G06F13/4269

    摘要： A structure and associated method to control a flow of data on a semiconductor device. A transmitter, receiver and transmission line are formed within the semiconductor device. The transmitter, receiver, and transmission line are adapted to control data transfer between a first core and a second core within the semiconductor device. The transmitter is adapted to send a signal over the transmission line to the receiver adapted to receive the signal. The receiver is further adapted to create an impedance mismatch to indicate that the second core is unable to transfer the data. The transmitter is adapted to detect the impedance mismatch.

    摘要翻译： 一种用于控制半导体器件上的数据流的结构和相关方法。 在半导体器件内形成发射器，接收器和传输线。 发射器，接收器和传输线适于控制半导体器件内的第一芯和第二芯之间的数据传输。 发射机适于通过传输线路将信号发送到适于接收信号的接收机。 接收机还适于产生阻抗失配以指示第二核心不能传送数据。 发射机适用于检测阻抗失配。

    Dynamic energy management
    13.
    发明授权
    Dynamic energy management 有权
    动态能源管理

    公开(公告)号：US08549330B2

    公开(公告)日：2013-10-01

    申请号：US12641578

    申请日：2009-12-18

    申请人： Paul Niekrewicz ,  Pascal A. Nsame ,  Aydin Suren ,  Sebastian Ventrone

    发明人： Paul Niekrewicz ,  Pascal A. Nsame ,  Aydin Suren ,  Sebastian Ventrone

    IPC分类号： G06F1/00

    CPC分类号： G06F1/26 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24

    摘要： A computer system with reliable dynamic energy management includes a thread synchronized energy configurator, the thread synchronized energy configurator extending an instruction decoder of the computer system and the thread synchronized energy configurator is disposed to append an energy configuration field including energy configuration bits to pipeline control bits of instructions in the instruction decoder, a thread synchronized dynamic frequency shifter (DFS), the thread synchronized DFS disposed to set control signals indicative of a frequency shift both per thread and per pipeline, and a thread synchronized general purpose register (GPR) super scaler, wherein the GPR super scaler is disposed to optimize thread operation based upon the set control signals.

    摘要翻译： 具有可靠的动态能量管理的计算机系统包括螺纹同步的能量配置器，延伸计算机系统的指令解码器的线程同步能量配置器和线程同步的能量配置器被设置为将包括能量配置位的能量配置字段附加到流水线控制位 指令解码器中的指令，线程同步动态移频器（DFS），线程同步DFS被设置为设置指示每线程和每个线路的频移的控制信号，以及线程同步通用寄存器（GPR）超级缩放器 其中，GPR超级定标器被设置为基于所设置的控制信号来优化线程操作。

    Dynamic Energy Managment
    14.
    发明申请
    Dynamic Energy Managment 有权
    动态能源管理

    公开(公告)号：US20110154064A1

    公开(公告)日：2011-06-23

    申请号：US12641578

    申请日：2009-12-18

    申请人： Paul Niekrewicz ,  Pascal A. Nsame ,  Aydin Suren ,  Sebastian Ventrone

    发明人： Paul Niekrewicz ,  Pascal A. Nsame ,  Aydin Suren ,  Sebastian Ventrone

    IPC分类号： G06F1/00

    CPC分类号： G06F1/26 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24

    摘要： A computer system with reliable dynamic energy management includes a thread synchronized energy configurator, the thread synchronized energy configurator extending an instruction decoder of the computer system and the thread synchronized energy configurator is disposed to append an energy configuration field including energy configuration bits to pipeline control bits of instructions in the instruction decoder, a thread synchronized dynamic frequency shifter (DFS), the thread synchronized DFS disposed to set control signals indicative of a frequency shift both per thread and per pipeline, and a thread synchronized general purpose register (GPR) super scaler, wherein the GPR super scaler is disposed to optimize thread operation based upon the set control signals.

    摘要翻译： 具有可靠的动态能量管理的计算机系统包括螺纹同步的能量配置器，延伸计算机系统的指令解码器的线程同步能量配置器和线程同步的能量配置器被设置为将包括能量配置位的能量配置字段附加到流水线控制位 指令解码器中的指令，线程同步动态移频器（DFS），线程同步DFS被设置为设置指示每线程和每个线路的频移的控制信号，以及线程同步通用寄存器（GPR）超级缩放器 其中，GPR超级定标器被设置为基于所设置的控制信号来优化线程操作。

    TEST SYSTEM FOR INTEGRATED CIRCUITS
    15.
    发明申请
    TEST SYSTEM FOR INTEGRATED CIRCUITS 失效
    集成电路测试系统

    公开(公告)号：US20080091994A1

    公开(公告)日：2008-04-17

    申请号：US11955433

    申请日：2007-12-13

    申请人： Alvar Dean ,  Sebastian Ventrone

    发明人： Alvar Dean ,  Sebastian Ventrone

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2893 ,  G01R1/0408 ,  G01R31/318505 ,  G01R31/31932

    摘要： A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip by comparing outputs of chips with each other or with a golden chip. Failing Chips are disconnected from further testing and passing or failing chips are recorded.

    摘要翻译： 测试板包括用于连接到待测试的多个集成电路芯片的多个插座。 板上的测试控制装置打开至少一个测试引擎，同时测试多个芯片。 检查电路通过将芯片的输出相互比较或与金色芯片进行比较来验证每个芯片的功能。 失败的芯片与进一步的测试断开连接，并记录通过或失败的芯片。

    WIRING OPTIMIZATIONS FOR POWER
    16.
    发明申请
    WIRING OPTIMIZATIONS FOR POWER 有权
    电力接线优化

    公开(公告)号：US20080074147A1

    公开(公告)日：2008-03-27

    申请号：US11952544

    申请日：2007-12-07

    申请人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

    发明人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

    IPC分类号： H03K19/00 ,  G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

    摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

    摘要翻译： 一种用于设计电气布线结构的电气布线结构和计算机系统。 电气配线结构包括电线对。 线对包括第一线和第二线。 第二根电线被预定为三态。 线对具有不小于预先选择的最小相同方向切换概率phi，SD，MIN或/或具有相同方向的切换概率，每时钟周期 每个时钟周期的相反方向切换概率Φ不小于预先选择的最小相对方向切换概率φi，MIN 。 第一线和第二线满足至少一个数学关系，其涉及公平和平坦，其中，W SPACING 被定义为 第一线和第二线，以及公共被定义为第一线和第二线的公共行程长度。

    System and Method for Dynamically Managing Power Consumption of Integrated Circuitry
    18.
    发明申请
    System and Method for Dynamically Managing Power Consumption of Integrated Circuitry 有权
    动态管理集成电路功耗的系统与方法

    公开(公告)号：US20070255970A1

    公开(公告)日：2007-11-01

    申请号：US11774245

    申请日：2007-07-06

    申请人： Henry Hottelet ,  Sebastian Ventrone

    发明人： Henry Hottelet ,  Sebastian Ventrone

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/171 ,  Y02D10/172

    摘要： An integrated circuit (IC) chip containing a plurality of voltage islands containing corresponding functional blocks that can be selectively fenced, i.e., powered down, while saving the states of the corresponding inputs, and unfenced in order to manage power consumption of the chip. Each fencable functional block includes a power switch and state-saving circuitry for saving the state of the inputs to that functional block. A power modulation unit (PMU) generates fencing signals that control the power switches and state-saving circuitries so as to selectively fence the corresponding functional blocks. The PMU generates the fencing signals as a function of one or more operating arguments.

    摘要翻译： 一种集成电路（IC）芯片，其包含多个电压岛，其中包含相应的功能块，其可选择性地围挡，即断电，同时节省相应输入的状态，并且不受限制地管理芯片的功耗。 每个可用功能块包括电源开关和用于将输入状态保存到该功能块的状态保存电路。 功率调制单元（PMU）产生控制电源开关和省电电路的栅栏信号，以选择性地围绕对应的功能块。 PMU根据一个或多个操作参数生成围栏信号。

    SYSTEM AND METHOD FOR DYNAMICALLY MANAGING POWER CONSUMPTION OF INTEGRATED CIRCUITRY
    20.
    发明申请
    SYSTEM AND METHOD FOR DYNAMICALLY MANAGING POWER CONSUMPTION OF INTEGRATED CIRCUITRY 失效
    用于动态管理集成电路功耗的系统与方法

    公开(公告)号：US20060174149A1

    公开(公告)日：2006-08-03

    申请号：US10906017

    申请日：2005-01-31

    申请人： Henry Hottelet ,  Sebastian Ventrone

    发明人： Henry Hottelet ,  Sebastian Ventrone

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/171 ,  Y02D10/172

    摘要： An integrated circuit (IC) chip (100) containing a plurality of voltage islands (124I-M) containing corresponding functional blocks (104I-M) that can be selectively fenced, i.e., powered down, while saving the states of the corresponding inputs, and unfenced in order to manage power consumption of the chip. Each fencable functional block includes a power switch (140I-M) and state-saving circuitry (148I-M) for saving the state of the inputs to that functional block. A power modulation unit (PMU) (132) generates fencing signals (144I-M) that control the power switches and state-saving circuitries so as to selectively fence the corresponding functional blocks. The PMU generates the fencing signals as a function of one or more operating arguments.

    摘要翻译： 一种集成电路（IC）芯片（100），其包含多个电压岛（124MIM），其包含相应的功能块（104IM），所述多个电压岛可被有选择地围栏，即断电，同时节省相应的输入的状态， 以便管理芯片的功耗。 每个可变功能块包括用于将输入状态保存到该功能块的电源开关（140I-M）和状态保存电路（148I-M）。 功率调制单元（PMU）（132）产生控制电源开关和省电电路的栅栏信号（144I-M），以选择性地围绕对应的功能块。 PMU根据一个或多个操作参数生成围栏信号。