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    Digital reliability monitor having autonomic repair and notification capability
    3.
    发明申请
    Digital reliability monitor having autonomic repair and notification capability 审中-公开
    数字可靠性监控器具有自主修复和通知功能

    公开(公告)号：US20050144524A1

    公开(公告)日：2005-06-30

    申请号：US10863194

    申请日：2004-06-08

    申请人： Anthony Bonaccio ,  Michael LeStrange ,  William Tonti ,  Sebastian Ventrone

    发明人： Anthony Bonaccio ,  Michael LeStrange ,  William Tonti ,  Sebastian Ventrone

    IPC分类号： G06F1/04 ,  G06F11/00

    CPC分类号： G06F1/04

    摘要： A method a circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter adapted to count pulses of a pulsed signal, the repair processor adapted to (a) replace the original circuit with a first redundant circuit or (b) adapted to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of predetermined cycle counts.

    摘要翻译： 一种用于防止集成电路中的故障的电路的方法。 电路包括：原电路; 一个或多个冗余电路; 以及修复处理器，包括适于计数脉冲信号的脉冲的时钟周期计数器，所述修复处理器适于（a）用第一冗余电路替换原始电路，或（b）适于选择另一个冗余电路， 从第二冗余电路到最后一个冗余电路的序列，并且每次循环计数器达到一组预定循环计数的预定计数时，用选定的冗余电路替换先前选择的冗余电路。

    Programmable capacitors and methods of using the same
    6.
    发明申请
    Programmable capacitors and methods of using the same 有权
    可编程电容器及其使用方法

    公开(公告)号：US20070188249A1

    公开(公告)日：2007-08-16

    申请号：US11353516

    申请日：2006-02-14

    申请人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

    发明人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

    IPC分类号： H03B5/12

    CPC分类号： H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03L7/095 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

    摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种调整半导体器件的电容的方法。 第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在 将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。 提供了许多其他方面。

    Memory elements and methods of using the same
    7.
    发明申请
    Memory elements and methods of using the same 失效
    内存元素和使用方法

    公开(公告)号：US20070189076A1

    公开(公告)日：2007-08-16

    申请号：US11353493

    申请日：2006-02-14

    申请人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

    发明人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0466

    摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。 控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由 存储元件在第一模式下操作。 提供了许多其他方面。

    FPGA POWERUP TO KNOWN FUNCTIONAL STATE
    9.
    发明申请
    FPGA POWERUP TO KNOWN FUNCTIONAL STATE 失效
    FPGA电源到已知的功能状态

    公开(公告)号：US20080030226A1

    公开(公告)日：2008-02-07

    申请号：US11869921

    申请日：2007-10-10

    申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

    发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17776 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/17772

    摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

    摘要翻译： 包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。 非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

    DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE
    10.
    发明申请
    DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE 有权
    基于充电储存装置的可能性确定使用数据保留装置的相对数量

    公开(公告)号：US20070258305A1

    公开(公告)日：2007-11-08

    申请号：US11279639

    申请日：2006-04-13

    申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

    发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

    IPC分类号： G11C7/00

    CPC分类号： G06F12/121 ,  G06F12/122

    摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

    摘要翻译： 公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。