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    METHODS FOR CONSERVING MEMORY IN STATISTICAL STATIC TIMING ANALYSIS
    11.
    发明申请
    METHODS FOR CONSERVING MEMORY IN STATISTICAL STATIC TIMING ANALYSIS 有权
    在统计静态时序分析中保存记忆的方法

    公开(公告)号：US20090241078A1

    公开(公告)日：2009-09-24

    申请号：US12053887

    申请日：2008-03-24

    申请人： Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method is provided for memory conservation in statistical static timing analysis. A timing graph is created with a timing run in a statistical static timing analysis program. A plurality of nodes in the timing graph that are candidates for a partial store and constraint points are identified. Timing data is persistently stored at constraint points. The persistent timing data is retrieved from the constraint points and used to calculate intermediate timing data at the plurality of nodes during timing analysis.

    摘要翻译： 在统计静态时序分析中提供了一种用于存储器保存的方法。 在统计静态时序分析程序中使用时序运行创建时序图。 识别作为部分存储和约束点的候选的定时图中的多个节点。 定时数据被持久存储在约束点。 从约束点检索持续定时数据，并用于在定时分析期间计算多个节点处的中间定时数据。

    Methods for conserving memory in statistical static timing analysis
    12.
    发明授权
    Methods for conserving memory in statistical static timing analysis 有权
    统计静态时序分析中保存记忆的方法

    公开(公告)号：US07849429B2

    公开(公告)日：2010-12-07

    申请号：US12053887

    申请日：2008-03-24

    申请人： Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5031

    摘要： A method is provided for memory conservation in statistical static timing analysis. A timing graph is created with a timing run in a statistical static timing analysis program. A plurality of nodes in the timing graph that are candidates for a partial store and constraint points are identified. Timing data is persistently stored at constraint points. The persistent timing data is retrieved from the constraint points and used to calculate intermediate timing data at the plurality of nodes during timing analysis.

    摘要翻译： 在统计静态时序分析中提供了一种用于存储器保存的方法。 在统计静态时序分析程序中使用时序运行创建时序图。 识别作为部分存储和约束点的候选的定时图中的多个节点。 定时数据被持久存储在约束点。 从约束点检索持续定时数据，并用于在定时分析期间计算多个节点处的中间定时数据。

    ADAPTIVE POWER CONTROL USING TIMING CANONICALS
    14.
    发明申请
    ADAPTIVE POWER CONTROL USING TIMING CANONICALS 有权
    使用时代标准的自适应功率控制

    公开(公告)号：US20140074422A1

    公开(公告)日：2014-03-13

    申请号：US13614564

    申请日：2012-09-13

    申请人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

    发明人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G01R31/317

    CPC分类号： G01R31/31718 ,  G01R31/3008

    摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

    摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非瞬时存储介质存储电压仓的边界作为速度分组测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

    Adaptive power control using timing canonicals
    16.
    发明授权
    Adaptive power control using timing canonicals 有权
    使用定时规范的自适应功率控制

    公开(公告)号：US09157956B2

    公开(公告)日：2015-10-13

    申请号：US13614564

    申请日：2012-09-13

    申请人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

    发明人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

    IPC分类号： G06F17/50 ,  G01R31/317 ,  G01R31/30

    CPC分类号： G01R31/31718 ,  G01R31/3008

    摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

    摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非瞬时存储介质存储电压仓的边界作为速度分组测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

    Method and apparatus for efficient incremental statistical timing analysis and optimization
    17.
    发明授权
    Method and apparatus for efficient incremental statistical timing analysis and optimization 有权
    用于高效增量统计时序分析和优化的方法和装置

    公开(公告)号：US08104005B2

    公开(公告)日：2012-01-24

    申请号：US12244512

    申请日：2008-10-02

    申请人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

    摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.

    摘要翻译： 在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。 给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是 在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值 根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值 改变了。

    Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis
    18.
    发明申请
    Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis 有权
    在统计静态时序分析中测量时钟偏移对松弛影响的方法

    公开(公告)号：US20120047477A1

    公开(公告)日：2012-02-23

    申请号：US12857591

    申请日：2010-08-17

    申请人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof.

    摘要翻译： 计算时钟偏差对统计松弛的影响，存在统计上可变的时序量，这些时间量占时钟树共同部分的公共路径信誉，以及时钟树非共同的RSS信用。 时钟偏移在每个发射和捕获路径对的基础上测量，作为后CPPR路径特定松弛（包括RSS信用），锁存到锁存延迟的总平均值，随机锁存的RSS值的函数 到锁定延迟，测试保护时间和测试调整。 该方法包括：执行初始的基于块的SSTA，包括CPPR分析; 选择至少一个启动和捕获路径对进行​​偏差分析; 对于至少一个路径对，记录后CPPR松弛，锁存到锁存延迟的总平均值，锁存器的RSS值到锁存延迟，测试保护时间和测试调整; 并量化时钟偏移对其统计松弛的影响。

    Method, system, and program product for accommodating spatially-correlated variation in a process parameter
    19.
    发明授权
    Method, system, and program product for accommodating spatially-correlated variation in a process parameter 失效
    用于在过程参数中适应空间相关变化的方法，系统和程序产品

    公开(公告)号：US07212946B1

    公开(公告)日：2007-05-01

    申请号：US11272234

    申请日：2005-11-10

    申请人： Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Lizheng Zhang ,  Vladimir Zolotov

    发明人： Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Lizheng Zhang ,  Vladimir Zolotov

    IPC分类号： G06F17/18 ,  G06F15/00 ,  G06F19/00

    CPC分类号： G06F17/5031

    摘要： The invention provides a method, system, and program product for accommodating spatially-correlated variation in a process parameter during statistical timing of a circuit. In one embodiment, the method includes dividing an area of the circuit into a plurality of grid cells; associating an independent random variable with each of the plurality of grid cells; and expressing at least one spatially-correlated parameter of a first grid cell as a function of the random variables associated with the first grid cell and at least one neighboring grid cell.

    摘要翻译： 本发明提供一种用于在电路的统计定时期间适应处理参数的空间相关变化的方法，系统和程序产品。 在一个实施例中，该方法包括将电路的区域划分成多个网格单元; 将独立随机变量与所述多个网格单元中的每一个相关联; 以及将与第一网格单元和至少一个相邻网格单元相关联的随机变量的函数表达为第一网格单元的至少一个空间相关参数。

    METHOD, SYSTEM, AND PROGRAM PRODUCT FOR ACCOMMODATING SPATIALLY-CORRELATED VARIATION IN A PROCESS PARAMETER
    20.
    发明申请
    METHOD, SYSTEM, AND PROGRAM PRODUCT FOR ACCOMMODATING SPATIALLY-CORRELATED VARIATION IN A PROCESS PARAMETER 失效
    方法，系统和程序产品，适用于过程参数中的空间相关变化

    公开(公告)号：US20070118331A1

    公开(公告)日：2007-05-24

    申请号：US11272234

    申请日：2005-11-10

    申请人： Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Lizheng Zhang ,  Vladimir Zolotov

    发明人： Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Lizheng Zhang ,  Vladimir Zolotov

    IPC分类号： G06F17/18

    CPC分类号： G06F17/5031

    摘要： The invention provides a method, system, and program product for accommodating spatially-correlated variation in a process parameter during statistical timing of a circuit. In one embodiment, the method includes dividing an area of the circuit into a plurality of grid cells; associating an independent random variable with each of the plurality of grid cells; and expressing at least one spatially-correlated parameter of a first grid cell as a function of the random variables associated with the first grid cell and at least one neighboring grid cell.

    摘要翻译： 本发明提供一种用于在电路的统计定时期间适应处理参数的空间相关变化的方法，系统和程序产品。 在一个实施例中，该方法包括将电路的区域划分成多个网格单元; 将独立随机变量与所述多个网格单元中的每一个相关联; 以及将与第一网格单元和至少一个相邻网格单元相关联的随机变量的函数表达为第一网格单元的至少一个空间相关参数。