公开(公告)号：US5999014A

公开(公告)日：1999-12-07

申请号：US932307

申请日：1997-09-17

申请人： Neil G. Jacobson ,  Matthew T. Murphy

发明人： Neil G. Jacobson ,  Matthew T. Murphy

IPC分类号： G06F17/50 ,  G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F17/5054

摘要： An improved method for concurrently programming in-system programmable logic devices (PLDs). More specifically, where within a plurality of serially connected PLDs, there are devices having different numbers of programmable memory cells, and devices whose memory cells require different wait periods to carry out programming, the method herein provides more optimum time efficiency and uses significantly less time overall for programming, erasing or reading back the PLDs. Also, the invention accommodates the implementation of retries to assure complete programming or erasing even when the initial attempt is not entirely successful. The method provides steps for accommodating PLDs with different wait times by bypassing fully programmed devices and speeding up programming times after smaller and slower devices are programmed and larger and faster devices are still not fully programmed. The method employs the step of altering the program implementation from concurrent to sequential programming to optimize retry efficiency.

摘要翻译： 一种用于同时编程系统可编程逻辑器件（PLD）的改进方法。 更具体地说，在多个串行连接的PLD中，存在具有不同数量的可编程存储器单元的器件以及其存储器单元需要不同等待周期来执行编程的器件，本文中的方法提供更优化的时间效率并且使用明显更少的时间 整体用于编程，擦除或读回PLD。 此外，本发明适用于重试的实现，以确保即使初始尝试不完全成功也能完全编程或擦除。 该方法提供了通过绕过完全编程的设备来容纳具有不同等待时间的PLD的步骤，并且在编程较小和较慢的设备之后加快编程时间，并且更大和更快的设备仍未被完全编程。 该方法采用将程序实现从并发改为顺序编程的步骤，以优化重试效率。

公开(公告)号：US5694399A

公开(公告)日：1997-12-02

申请号：US631766

申请日：1996-04-10

申请人： Neil G. Jacobson ,  Anthony S. Maraldo

发明人： Neil G. Jacobson ,  Anthony S. Maraldo

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318572

摘要： A system for interfacing with a test access communication port. Specifically, the present invention has application to the IEEE 1149.1 Test Access Port ("JTAG") standard. The novel system includes a hardware unit having a memory unit and a special processor unit (SPU) that interfaces between the test access port and components of a general purpose host computer system. The host computer system uses software procedures to formulate a set of compressed instructions instructing the hardware unit to generate and/or receive signals in connection with the test access port. In one embodiment, the host computer system contains configuration data in a special format. The host computer system translates this configuration data into the compressed instructions which are transmitted to the hardware unit causing it to download the configuration data using signals recognized by the test access port. The data is downloaded into a programmable integrated circuit device using the test access port. The SPU contains circuitry to expand the compressed instruction to generate the appropriate driving and receiving signals of the test access port. In one embodiment, clock, state machine, and data-in signals are generated by the SPU while a data-out signal can be received and relayed to the host computer system. The host computer system can be of a number of well known platforms (e.g., x86, DEC Alpha, Power PC, Mips, RISC, etc.).

摘要翻译： 用于与测试访问通信端口进行接口的系统。 具体地说，本发明适用于IEEE 1149.1测试接入端口（“JTAG”）标准。 该新颖系统包括具有存储器单元和在测试访问端口和通用主机计算机系统的组件之间进行接口的特殊处理器单元（SPU）的硬件单元。 主计算机系统使用软件程序来制定一组压缩指令，指示硬件单元产生和/或接收与测试访问端口相关的信号。 在一个实施例中，主计算机系统包含特殊格式的配置数据。 主计算机系统将该配置数据转换成被发送到硬件单元的压缩指令，使其使用由测试访问端口识别的信号来下载配置数据。 使用测试访问端口将数据下载到可编程集成电路设备中。 SPU包含扩展压缩指令以产生测试访问端口的适当驱动和接收信号的电路。 在一个实施例中，时钟，状态机和数据输入信号由SPU产生，同时可以接收数据输出信号并将其中继到主计算机系统。 主计算机系统可以是许多众所周知的平台（例如，x86，DEC Alpha，Power PC，Mips，RISC等）。

公开(公告)号：US07610534B1

公开(公告)日：2009-10-27

申请号：US11725664

申请日：2007-03-20

申请人： Neil G. Jacobson

发明人： Neil G. Jacobson

IPC分类号： G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/318558

摘要： Methods and systems are provided for determining a total length of instruction registers. A data shift of a scan chain determines whether each device in the scan chain is an identified device. An overall length of the instruction registers of the devices is determined from an instruction shift. An actual position is determined for an identified device between each pair of sub-sequences of unidentified devices. An instruction shift of the scan chain attempts to set the respective instruction register of the identified device using one or more trial positions. If a data shift of the scan chain obtains the recognized value of the respective identification register of the identified device for one of the trial positions, then this trial position is the actual position within the overall length. The total length is determined for the instruction registers of the unidentified devices in each sub-sequence of the unidentified devices.

摘要翻译： 提供了用于确定指令寄存器总长度的方法和系统。 扫描链的数据移位确定扫描链中的每个设备是否是识别的设备。 根据指令移位确定设备的指令寄存器的总长度。 确定在未识别设备的每对子序列之间的已识别设备的实际位置。 扫描链的指令移位尝试使用一个或多个试用位置来设置所识别的设备的相应指令寄存器。 如果扫描链的数据移位获得了针对一个试验位置的所识别的装置的相应识别寄存器的识别值，则该试验位置是整个长度内的实际位置。 为未识别设备的每个子序列中的未识别设备的指令寄存器确定总长度。

公开(公告)号：US07428674B1

公开(公告)日：2008-09-23

申请号：US11333973

申请日：2006-01-17

申请人： Neil G. Jacobson

发明人： Neil G. Jacobson

IPC分类号： G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/318555

摘要： Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitoring the state vector includes a TAP controller, a storage circuit, and a sampling circuit. The TAP controller updates the state vector for each transition of TCK. The storage circuit stores a value of the state vector responsive to transitions of TCK while a write enable is enabled. To permit generating the write enable without additional pins and without violating a protocol for the test access port, the write enable may be generated in response to a plurality of transitions of TDI of the test access port during an interval in which TMS and TCK of the test access port have no transitions.

摘要翻译： 监视测试访问端口（TAP）的状态向量允许由于各种因素（包括电气噪声）而隔离状态向量的不当转换的根本原因。 测试访问端口包括TCK，TMS，TDI和TDO。 用于监视状态矢量的电路包括TAP控制器，存储电路和采样电路。 TAP控制器更新TCK每个转换的状态向量。 存储电路在启用写使能的同时存储响应于TCK的转变的状态向量的值。 为了允许在没有附加引脚的情况下生成写入使能，并且在不违反测试接入端口的协议的情况下，可以响应于测试接入端口的TDI的多个转换在其间的TMS和TCK的间隔期间生成写入使能 测试访问端口没有转换。

公开(公告)号：US07133822B1

公开(公告)日：2006-11-07

申请号：US09823154

申请日：2001-03-29

申请人： Neil G. Jacobson

发明人： Neil G. Jacobson

IPC分类号： G06F9/455 ,  H03K17/693

CPC分类号： G06F11/366 ,  G06F11/2294

摘要： A system and method for diagnosing an electronic device remotely using a network is provided. The electronic device includes one or more programmable logic devices that are configurable. A diagnostic microcontroller functions to communicate to the programmable logic devices and to communicate to the network. To diagnose the electronic device, communication is established to the network and to a diagnostic/repair center. The diagnostic/repair center selects diagnostic commands and transmits them to the electronic device. The diagnostic microcontroller initiates the diagnostic commands on the one or more programmable logic devices to test their configuration and/or functionality. Test results are collected and transmitted back to the diagnostic/repair center for analysis. Based on the analysis, if appropriate, reconfiguration commands are sent to reconfigure the programmable logic device to correct identified errors.

摘要翻译： 提供了一种使用网络远程诊断电子设备的系统和方法。 电子设备包括可配置的一个或多个可编程逻辑设备。 诊断微控制器用于与可编程逻辑器件通信并与网络进行通信。 要诊断电子设备，建立通信到网络和诊断/维修中心。 诊断/维修中心选择诊断命令并将其发送到电子设备。 诊断微控制器启动一个或多个可编程逻辑器件上的诊断命令，以测试其配置和/或功能。 收集测试结果并传回诊断/维修中心进行分析。 基于分析，如果合适，发送重新配置命令以重新配置可编程逻辑器件以纠正识别的错误。

公开(公告)号：US06915518B1

公开(公告)日：2005-07-05

申请号：US09626300

申请日：2000-07-24

申请人： Neil G. Jacobson

发明人： Neil G. Jacobson

IPC分类号： G06G9/46

CPC分类号： G06F9/5088 ,  G06F9/505 ,  G06F9/5061 ,  G06F2209/5022

摘要： A system and method for allocating resources of programmable logic devices (PLDs) according to activity level. In various embodiments, the activity levels of functions implemented on the PLDs are monitored. When decreasing and/or increasing activity levels are detected, the PLD resources are reallocated between the various functions in proportion to the decreasing and/or increasing activity levels.

摘要翻译： 一种根据活动级别分配可编程逻辑器件（PLD）资源的系统和方法。 在各种实施例中，监视在PLD上实现的功能的活动水平。 当检测到降低和/或增加活动水平时，PLD资源在各种功能之间按比例减少和/或增加的活动水平重新分配。

公开(公告)号：US06714040B1

公开(公告)日：2004-03-30

申请号：US10162240

申请日：2002-06-03

申请人： Neil G. Jacobson ,  Emigdio M. Flores, Jr. ,  Sanjay Srivastava ,  Bin Dai ,  Sungnien Jerry Mao

发明人： Neil G. Jacobson ,  Emigdio M. Flores, Jr. ,  Sanjay Srivastava ,  Bin Dai ,  Sungnien Jerry Mao

IPC分类号： H03K19177

CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/17764 ,  H03K19/17768

摘要： A method for programming a series of in-system programmable devices that uses Boundary-Scan techniques to read device identification codes from each device of a system, and to automatically generate a board/device information file including a record for each device arranged in the order in which the devices are chained in the system. The device identification codes are then used to automatically retrieve device specifications from a central database. When no identification code is provided from the device, or the database fails to include specifications for a particular device, the user is prompted to enter minimum information or specifications necessary to carry out communications with the device. After device specifications are entered for each device, the user is prompted to enter configuration data, which is automatically matched to its associated device, and compared for consistency with the device specifications. After verifying the configuration data, programming is performed using the configuration data.

摘要翻译： 一种用于对使用边界扫描技术从系统的每个设备读取设备识别码的一系列在系统可编程设备进行编程的方法，并且自动生成包括按照顺序排列的每个设备的记录的电路板/设备信息文件 其中设备被链接在系统中。 然后，设备标识码用于从中央数据库自动检索设备规格。 当没有从设备提供识别码，或者数据库不能包括特定设备的规范时，提示用户输入与设备进行通信所必需的最小信息或规格。 在为每个设备输入设备规格后，将提示用户输入配置数据，并自动匹配其相关设备，并与设备规格进行比较。 验证配置数据后，使用配置数据进行编程。

公开(公告)号：US06571382B1

公开(公告)日：2003-05-27

申请号：US09758597

申请日：2001-01-10

申请人： Neil G. Jacobson ,  Matthew T. Murphy

发明人： Neil G. Jacobson ,  Matthew T. Murphy

IPC分类号： G06F1750

CPC分类号： G06F17/5054

摘要： A method and apparatus are disclosed for reducing the likelihood of unintentionally or irreversibly activating one or more of a programmable logic device's output elements after a programming interruption. Output disable and enable bits are moved to near the beginning and end, respectively, of a programming bitstream, thereby maximizing the amount of time the device outputs are in high impedance mode during programming, and minimizing the risk of unintentionally driving the device outputs.

摘要翻译： 公开了一种用于在编程中断之后降低无意或不可逆地激活可编程逻辑器件的输出元件中的一个或多个的可能性的方法和装置。 输出禁止和使能位分别移动到编程比特流的开始和结束附近，从而最大限度地减少编程期间器件输出处于高阻抗模式的时间量，并最大限度地减少无意驱动器件输出的风险。

公开(公告)号：US07669102B1

公开(公告)日：2010-02-23

申请号：US11514425

申请日：2006-09-01

申请人： Wayne E. Wennekamp ,  Randal Kuramoto ,  James A. Walstrum, Jr. ,  Sanja Srivastava ,  Neil G. Jacobson

发明人： Wayne E. Wennekamp ,  Randal Kuramoto ,  James A. Walstrum, Jr. ,  Sanja Srivastava ,  Neil G. Jacobson

IPC分类号： G01R31/28 ,  G06F7/38 ,  H03K19/173 ,  G06F13/00

CPC分类号： G11C29/48 ,  G11C29/1201 ,  G11C2029/0401 ,  G11C2029/5602 ,  H03K19/1776

摘要： A memory coupled to a programmable logic device (PLD) is configured through the PLD's JTAG port. A soft core loaded into the PLD connects to the JTAG port and memory. An external programming host device connects to the JTAG port, sends instructions and data to and receives data from the memory via the JTAG port and soft core. A synchronization JTAG instruction is loaded, and a Shift Data state of the JTAG port state machine is used. The programming host device and soft core are synchronized, and a memory chip select is asserted. A memory instruction, such as READ, WRITE or ERASE is loaded into the memory. An RTI state of the state machine is used to wait for instruction completion and the chip select is deasserted. Another instruction is processed starting with using the Shift Data state. Alternatively, a PLD Shift Data Register is used in conjunction with the soft core.

摘要翻译： 通过PLD的JTAG端口配置与可编程逻辑器件（PLD）耦合的存储器。 加载到PLD的软核连接到JTAG端口和存储器。 一个外部编程主机设备连接到JTAG端口，通过JTAG端口和软核向内存发送指令和数据并从存储器接收数据。 加载同步JTAG指令，并使用JTAG端口状态机的移位数据状态。 编程主机设备和软核同步，存储芯片选择被断言。 诸如READ，WRITE或ERASE之类的存储器指令被加载到存储器中。 状态机的RTI状态用于等待指令完成，芯片选择被置为无效。 从使用Shift Data状态开始处理另一条指令。 或者，PLD移位数据寄存器与软核一起使用。

公开(公告)号：US07581124B1

公开(公告)日：2009-08-25

申请号：US11326542

申请日：2006-01-04

申请人： Neil G. Jacobson ,  Matthew T. Murphy ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

发明人： Neil G. Jacobson ,  Matthew T. Murphy ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC分类号： G06F1/22

CPC分类号： G11C5/14 ,  G11C5/148 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0401 ,  H03K19/17784

摘要： A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.

摘要翻译： PLD包括多个逻辑块，测试电路和测试引脚组。 逻辑块耦合到选通电路，门电路响应于控制信号选择性地调整块的工作电压。 在PLD的操作期间，响应于通过测试引脚设置到PLD的外部产生的信号来更新控制信号，并使用测试电路将其传送到逻辑块。