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    Disabling unused/inactive resources in an integrated circuit for static power reduction
    2.
    发明授权
    Disabling unused/inactive resources in an integrated circuit for static power reduction 有权
    禁用集成电路中的未使用/不活动资源以实现静态功耗降低

    公开(公告)号：US08099691B1

    公开(公告)日：2012-01-17

    申请号：US12491174

    申请日：2009-06-24

    申请人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    发明人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    IPC分类号： G06F17/50

    CPC分类号： H03K19/17784

    摘要： A method of operating an integrated circuit (“IC”) is disclosed. The method includes identifying one or more unused or inactive resources of the IC which will not be used in a circuit design or which are inactive during operation of the IC. The method also includes enabling resources of the IC which will be used in the circuit design, and also disabling one or more unused or inactive resources of the IC from one or more power supply terminals in response to configuration values which are stored in memory cells.

    摘要翻译： 公开了一种操作集成电路（“IC”）的方法。 该方法包括识别不在电路设计中使用的IC中的一个或多个未使用或非活动资源，或者在IC运行期间不活动的资源。 该方法还包括启用将用于电路设计中的IC的资源，以及响应于存储在存储单元中的配置值，从一个或多个电源端子禁用IC的一个或多个未使用或不活动的资源。

    Tuning programmable logic devices for low-power design implementation
    3.
    发明授权
    Tuning programmable logic devices for low-power design implementation 有权
    调整可编程逻辑器件，实现低功耗设计

    公开(公告)号：US07549139B1

    公开(公告)日：2009-06-16

    申请号：US10783216

    申请日：2004-02-20

    申请人： Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

    发明人： Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

    IPC分类号： G06F17/50 ,  H03K19/00

    CPC分类号： H03K19/17784 ,  G11C5/14 ,  H03K3/356173 ,  H03K19/0016 ,  H03K19/17792

    摘要： A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.

    摘要翻译： 一种操作可编程逻辑器件的方法包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的第一组有源块，并使用降低的电源电压（例如，0.9Vd）来操作第二组 可编程逻辑器件的有源块。 执行时序分析以确定每个活动块中的最大可用时序松弛。 具有较小定时松弛的有源块被分组在第一组中，并且被耦合以接收完整的VDD电源电压。 具有较大定时松弛的有源块被分组在第二组中，并被耦合以接收降低的VDD电源电压。 结果，第二组中的活动块表现出降低的功耗，而不会对可编程逻辑器件的总速度产生不利影响。

    Disabling unused/inactive resources in programmable logic devices for static power reduction
    4.
    发明授权
    Disabling unused/inactive resources in programmable logic devices for static power reduction 有权

    公开(公告)号：US07098689B1

    公开(公告)日：2006-08-29

    申请号：US10666669

    申请日：2003-09-19

    申请人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    发明人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    IPC分类号： H03K19/094 ,  H03K19/177 ,  G05F1/10 ,  G11C5/14

    CPC分类号： H03K19/17784

    摘要： A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

    Disabling unused/inactive resources in programmable logic devices for static power reduction
    5.
    发明授权
    Disabling unused/inactive resources in programmable logic devices for static power reduction 有权
    禁用可编程逻辑器件中的未使用/不活动资源以实现静态功耗降低

    公开(公告)号：US07562332B1

    公开(公告)日：2009-07-14

    申请号：US11502939

    申请日：2006-08-11

    申请人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    发明人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    IPC分类号： G06F17/50

    CPC分类号： H03K19/17784

    摘要： A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

    摘要翻译： 一种操作可编程逻辑器件的方法，包括以下步骤：使可编程逻辑器件的资源在由可编程逻辑器件实现的电路设计中使用，以及禁用未被使用的可编程逻辑器件的未使用或不活动资源 电路设计。 禁用的步骤可以包括从一个或多个电源端子去耦合未使用或不活动的资源。 或者，禁用步骤可以包括调节施加到未使用或不活动资源的电源电压。 可以响应于由可编程逻辑器件存储的配置数据位和/或响应于用户控制的信号来执行禁用步骤。 可以在可编程逻辑器件的设计时间和/或运行时间期间启动禁用步骤。

    Regulating unused/inactive resources in programmable logic devices for static power reduction
    6.
    发明授权
    Regulating unused/inactive resources in programmable logic devices for static power reduction 有权
    调节可编程逻辑器件中的未使用/不活动资源以实现静态功耗的降低

    公开(公告)号：US07504854B1

    公开(公告)日：2009-03-17

    申请号：US10783589

    申请日：2004-02-20

    申请人： Kevin T. Look ,  Michael J. Hart ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    发明人： Kevin T. Look ,  Michael J. Hart ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    IPC分类号： H03K19/173 ,  G11C5/14

    CPC分类号： H03K19/1778 ,  G11C5/14 ,  H03K19/17784

    摘要： A method of operating a programmable logic device, including the steps of using a full VDD supply voltage to operate one or more active blocks of the programmable logic device, and using a reduced supply voltage (e.g., ½ VDD) to operate one or more inactive blocks of the programmable logic device. The full VDD supply voltage and reduced supply voltage can be provided to the blocks of the programmable logic device through high-voltage n-channel transistors. A boosted voltage, greater than VDD, is applied to the gate of an n-channel transistor to provide the full VDD supply voltage to an active block. A standby voltage, less than VDD, is applied to the gate of an n-channel transistor to provide the reduced supply voltage to an inactive block. The inactive blocks can be determined during run time and/or design time of the programmable logic device.

    摘要翻译： 一种操作可编程逻辑器件的方法，包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的一个或多个有效块，以及使用降低的电源电压（例如，½VDD）来操作一个或多个不活动的 可编程逻辑器件的块。 可以通过高电压n沟道晶体管向可编程逻辑器件的块提供完整的VDD电源电压和降低的电源电压。 大于VDD的升压电压被施加到n沟道晶体管的栅极，以向有源块提供完整的VDD电源电压。 小于VDD的待机电压被施加到n沟道晶体管的栅极，以向非活动块提供降低的电源电压。 可以在可编程逻辑器件的运行时间和/或设计时间期间确定非活动块。

    Overridable data protection mechanism for PLDs
    7.
    发明授权
    Overridable data protection mechanism for PLDs 有权
    PLD可覆盖的数据保护机制

    公开(公告)号：US5991880A

    公开(公告)日：1999-11-23

    申请号：US190053

    申请日：1998-11-10

    申请人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

    发明人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

    IPC分类号： G06F12/14 ,  G06F21/00

    CPC分类号： G06F21/76 ,  G06F12/1466

    摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

    摘要翻译： 用于解锁/锁定PLD的可覆盖的数据保护机制包括数据保护覆盖键寄存器，输入键寄存器和比较器。 在用户向输入键寄存器输入访问代码之后，软件程序向比较器发送使能信号，该比较器进一步比较存储在数据保护覆盖键寄存器中的位与输入键寄存器中的位。 如果两个寄存器中的位相同，则比较器输出禁用数据保护信号，从而允许用户修改该PLD中的配置数据。 在增加的版本控制号码和新的配置数据被下载到PLD之后，程序向比较器发送禁用信号，从而防止对该PLD的配置数据的进一步修改。

    Series capacitor coupling multiplexer for programmable logic devices
    9.
    发明授权
    Series capacitor coupling multiplexer for programmable logic devices 失效
    用于可编程逻辑器件的串联电容耦合多路复用器

    公开(公告)号：US07046071B1

    公开(公告)日：2006-05-16

    申请号：US10633727

    申请日：2003-08-04

    申请人： Robert O. Conn ,  Kameswara K. Rao

    发明人： Robert O. Conn ,  Kameswara K. Rao

    IPC分类号： H03K17/62 ,  H03K17/693

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/1778 ,  H03K19/17796

    摘要： A series capacitor coupling (SCC) structure is controllable to capacitively couple a data input lead of the SCC structure to an output lead of the SCC, or to de-couple the data input lead from the data output lead. An SCC is controlled by a control bit stored in an associated memory cell. A multiplexer is fashioned out of a plurality of such SCC structures such that the edges of a digital signal received on a selected one of a plurality of multiplexer data input leads is coupled through the SCC structures onto an intervening node. The edges of the digital signal on the intervening node are then latched to recreate the incoming digital signal and the latched signal is output onto a multiplexer data output lead. The multiplexer is very fast and has a low leakage current in comparison to conventional transmission gate multiplexers used in programmable logic devices.

    摘要翻译： 串联电容耦合（SCC）结构是可控制的，以将SCC结构的数据输入引线电容耦合到SCC的输出引线，或者从数据输出引线去耦合数据输入引线。 SCC由存储在关联的存储单元中的控制位控制。 从多个这样的SCC结构中形成多路复用器，使得在多个多路复用器数据输入引线中的选定的一个上接收的数字信号的边缘通过SCC结构耦合到中间节点上。 然后中断节点上的数字信号的边沿被锁存以重建输入的数字信号，并且锁存的信号被输出到多路复用器数据输出引线上。 与可编程逻辑器件中使用的常规传输栅极复用器相比，多路复用器非常快，具有低漏电流。