公开(公告)号：US4967394A

公开(公告)日：1990-10-30

申请号：US241748

申请日：1988-09-08

申请人： Hidenobu Minagawa ,  Yuuichi Tatsumi ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

发明人： Hidenobu Minagawa ,  Yuuichi Tatsumi ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

IPC分类号： G11C16/08 ,  G11C16/28 ,  G11C16/32 ,  G11C16/34 ,  G11C29/24 ,  G11C29/50 ,  G11C29/52

CPC分类号： G11C29/50012 ,  G11C16/08 ,  G11C16/28 ,  G11C16/32 ,  G11C16/34 ,  G11C29/24 ,  G11C29/50 ,  G11C29/52 ,  G11C16/04

摘要： A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row and column conductive lines, a memory cell array including nonvolatile memory cells arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines and the power source lines, a first selector circuit for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line, and a dummy memory cells each having a source, a drain and a control gate connected to the dummy row line. In the semiconductor memory device, one of paths between the source and the power source line and between the drain and the corresponding row line is closed and the other path is opened, and it further includes a second selector circuit for selectively generating a line selection signal for selecting one of the row conductive lines in response to an address signal and a dummy selection signal for selecting the dummy row line in response to the same address signal.

公开(公告)号：US4916334A

公开(公告)日：1990-04-10

申请号：US226312

申请日：1988-07-29

申请人： Hidenobu Minagawa ,  Yuuichi Tatsumi ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

发明人： Hidenobu Minagawa ,  Yuuichi Tatsumi ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

IPC分类号： G11C16/30 ,  H02M3/07 ,  H03K5/02

CPC分类号： G11C16/30 ,  H02M3/07 ,  H03K5/023

摘要： A semiconductor integrated circuit includes a CMOS circuit operated on a voltage of a first voltage level to set an output node thereof to a voltage of the first voltage level or a reference voltage; an output circuit for controlling supply of a voltage of a second voltage level which is higher than the first voltage level to a signal output node; and an isolation MOS transistor having a current path connected between the output node of the CMOS circuit and the signal output node and a gate connected to receive a control signal. The output node of the CMOS circuit is set to the reference voltage with the conduction resistance of the isolation MOS transistor kept high after the lapse of period in which the voltage of the second voltage level is kept supplied to the signal output node. After this, the conduction resistance of the isolation MOS transistor is reduced in response to the control signal.

摘要翻译： 半导体集成电路包括以第一电压电平工作的CMOS电路，以将其输出节点设置为第一电压电平或参考电压的电压; 输出电路，用于控制向信号输出节点提供高于第一电压电平的第二电压电平的电压; 以及隔离MOS晶体管，其具有连接在CMOS电路的输出节点和信号输出节点之间的电流路径以及连接以接收控制信号的栅极。 CMOS电路的输出节点被设定为参考电压，其中隔离MOS晶体管的导通电阻保持高电平，其中第二电压电平的电压被保持提供给信号输出节点。 此后，隔离MOS晶体管的导通电阻响应于控制信号而减小。