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    Method for making asymmetric double-gate transistors
    14.
    发明授权
    Method for making asymmetric double-gate transistors 有权
    制造非对称双栅晶体管的方法

    公开(公告)号：US08399316B2

    公开(公告)日：2013-03-19

    申请号：US12521233

    申请日：2007-12-28

    申请人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    发明人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    IPC分类号： H01L21/00

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

    摘要： A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted.

    摘要翻译： 一种用于制造具有一个或多个双栅极晶体管的微电子器件的方法，包括：a）在衬底上形成一个或多个结构，所述衬底包括至少一个构造成形成双栅极晶体管的第一栅极的第一块，并且至少 配置成形成双栅极的第二栅极的第二块，第一块和第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区和第二栅极电介质与半导体区分离 区; 以及b）使用相对于所述第一块选择性的至少第一注入，在所述结构中掺杂至少一个给定结构的所述第二块中的至少一个或多个半导体区域，所述注入在给定结构的第一侧上进行 在通过半导电区域的衬底的主平面的法线的另一侧的结构的一部分未被植入。

    Memory cell provided with dual-gate transistors, with independent asymmetric gates
    15.
    发明授权
    Memory cell provided with dual-gate transistors, with independent asymmetric gates 有权
    具有双栅极晶体管的存储单元，具有独立的非对称栅极

    公开(公告)号：US08116118B2

    公开(公告)日：2012-02-14

    申请号：US12005666

    申请日：2007-12-26

    申请人： Olivier Thomas ,  Maud Vinet

    发明人： Olivier Thomas ,  Maud Vinet

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/785

    摘要： The invention concerns a random access memory cell comprising: at least one first plurality of symmetrical dual-gate transistors (TL1T, TL1F, TD1T, TD1F, TL2T, TL2F) forming a flip-flop, at least a first asymmetric dual-gate access transistor (TA1T, TAW1T) and at least a second asymmetric dual-gate access transistor (TA1F, TAW1F) disposed respectively between a first bit line (BLT, WBLT) and a first storage node (T), and between a second bit line (BLF, WBLF) and a second storage node (F), a first gate of the first access transistor (TA1T, TAW1T) and a first gate of the second access transistor (TA1F, TAW1F) being connected to a first word line (WL, WWL) able to route a biasing signal, a second gate (TA1F, TAW1F) of the first access transistor connected to the second storage node (F) and a second gate of the second access transistor connected to the first storage node (T).

    摘要翻译： 本发明涉及一种随机存取存储单元，包括：形成触发器的至少一个第一对称双栅极晶体管（TL1T，TL1F，TD1T，TD1F，TL2T，TL2F），至少第一不对称双栅极存取晶体管 （TA1T，TAW1T）和分别布置在第一位线（BLT，WBLT）和第一存储节点（T）之间以及第二位线（BLF）之间的至少第二非对称双栅极存取晶体管（TA1F，TAW1F） ，WBLF）和第二存储节点（F），第一存取晶体管的第一栅极（TA1T，TAW1T）和第二存取晶体管的第一栅极（TA1F，TAW1F）连接到第一字线（WL，WWL ）能够路由偏置信号，连接到第二存储节点（F）的第一存取晶体管的第二栅极（TA1F，TAW1F）和连接到第一存储节点（T）的第二存取晶体管的第二栅极。

    METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE
    16.
    发明申请
    METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE 有权
    用不对称和对称双栅极晶体管制造不对称双栅极晶体管的方法可以在同一基板上

    公开(公告)号：US20100320541A1

    公开(公告)日：2010-12-23

    申请号：US12521377

    申请日：2007-12-28

    申请人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    发明人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8244

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

    摘要： A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.

    摘要翻译： 一种用于制造具有一个或多个非对称双栅极晶体管的微电子器件的方法，包括：a）在至少包括形成双栅晶体管的第一栅极的第一半导体块的衬底上形成一个或多个结构，以及 至少第二半导体块，其被配置为形成所述双栅极晶体管的第二栅极，所述第一块和所述第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区与所述半导体区分离;以及 分别为第二栅极介电区，以及b）使用相对于第一块选择性的至少一种注入，在结构中的至少一个给定结构的第二块中至少掺杂一个或多个半导体区域。

    METHOD FOR MAKING ASYMMETRIC DOUBLE-GATE TRANSISTORS
    17.
    发明申请
    METHOD FOR MAKING ASYMMETRIC DOUBLE-GATE TRANSISTORS 有权
    制造非对称双栅极晶体管的方法

    公开(公告)号：US20100178743A1

    公开(公告)日：2010-07-15

    申请号：US12521233

    申请日：2007-12-28

    申请人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    发明人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

    摘要： A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted.

    摘要翻译： 一种用于制造具有一个或多个双栅极晶体管的微电子器件的方法，包括：a）在衬底上形成一个或多个结构，所述衬底包括至少一个构造成形成双栅极晶体管的第一栅极的第一块，并且至少 配置成形成双栅极的第二栅极的第二块，第一块和第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区和第二栅极电介质与半导体区分离 区; 以及b）使用相对于所述第一块选择性的至少第一注入，在所述结构中掺杂至少一个给定结构的所述第二块中的至少一个或多个半导体区域，所述注入在给定结构的第一侧上进行 在通过半导电区域的衬底的主平面的法线的另一侧的结构的一部分未被植入。

    SELF-CONTAINED INTEGRATED CIRCUIT HAVING TRANSISTORS WITH SEPARATE THRESHOLD VOLTAGES
    18.
    发明申请
    SELF-CONTAINED INTEGRATED CIRCUIT HAVING TRANSISTORS WITH SEPARATE THRESHOLD VOLTAGES 有权
    具有独立阈值电压的具有晶体管的自包含集成电路

    公开(公告)号：US20120126333A1

    公开(公告)日：2012-05-24

    申请号：US13262376

    申请日：2010-04-01

    申请人： Olivier Thomas ,  Jean-Philippe Noel

    发明人： Olivier Thomas ,  Jean-Philippe Noel

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203

    摘要： The invention relates to an integrated circuit including an active semiconducting layer separated from a semiconducting substrate layer by an embedded insulating material surface, including: first and second transistors (205, 213) of a single type; first and second floorplans arranged vertically perpendicular to the first and second transistors; wherein the first transistor has a doping of the floorplan thereof, opposite that of the source thereof, and a first threshold voltage; the second transistor has a doping of the floorplan thereof, identical to that of the source thereof, and a second threshold voltage; the first threshold voltage is dependent on the potential difference applied between the source and the floorplan of the first transistor; and the second threshold voltage is dependent on the potential difference applied between the source and the floorplan of the second transistor.

    摘要翻译： 本发明涉及一种集成电路，其包括通过嵌入式绝缘材料表面与半导体衬底层分离的有源半导体层，其包括：单一类型的第一和第二晶体管（205,213）; 垂直于第一和第二晶体管垂直排列的第一和第二平面图; 其中所述第一晶体管具有与其源极相反的其平面图的掺杂和第一阈值电压; 第二晶体管具有与其源极相同的其平面图的掺杂和第二阈值电压; 第一阈值电压取决于施加在第一晶体管的源极和平面布置图之间的电位差; 并且第二阈值电压取决于施加在第二晶体管的源极和平面布置图之间的电位差。

    SRAM MEMORY CELL PROVIDED WITH TRANSISTORS HAVING A VERTICAL MULTICHANNEL STRUCTURE
    19.
    发明申请
    SRAM MEMORY CELL PROVIDED WITH TRANSISTORS HAVING A VERTICAL MULTICHANNEL STRUCTURE 有权
    具有垂直多通道结构的晶体管的SRAM存储单元

    公开(公告)号：US20100264496A1

    公开(公告)日：2010-10-21

    申请号：US12740907

    申请日：2008-11-07

    申请人： Olivier Thomas ,  Thomas Ernst

    发明人： Olivier Thomas ,  Thomas Ernst

    IPC分类号： H01L27/11 ,  H01L21/8244

    CPC分类号： G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/78696

    摘要： A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k≧1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate.

    摘要翻译： 一种微电子器件，在衬底上包括诸如SRAM存储单元的至少一个元件; 分别包括在与衬底的主平面形成非零角度的方向上平行的k个通道（k≥1）和一个或多个第二晶体管的一个或多个第一晶体管 包括数个m个通道，使得与形成非零角度的方向或正交方向平行的m> k与衬底的主平面。

    Integrated Circuit with a Power Transistor Gate Bias Controlled by the Leakage Current
    20.
    发明申请
    Integrated Circuit with a Power Transistor Gate Bias Controlled by the Leakage Current 有权
    具有由漏电流控制的功率晶体管栅极偏置的集成电路

    公开(公告)号：US20100117720A1

    公开(公告)日：2010-05-13

    申请号：US12608616

    申请日：2009-10-29

    申请人： Alexandre Valentian ,  Olivier Thomas

    发明人： Alexandre Valentian ,  Olivier Thomas

    IPC分类号： G05F1/10

    CPC分类号： H03K19/0013 ,  H03K17/063 ,  H03K19/00384

    摘要： The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and of having, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a voltage step-up charge pump generates a gate bias voltage from pulses delivered by an oscillator having its frequency controlled by a current. The control current Ic is the leakage current of a transistor having technological characteristics similar to those of the power transistor. The system optimizes the current consumption in standby mode, the frequency of the oscillator being reduced when the gate is biased so as to minimize the leakage current. The invention is applicable to circuits powered by a battery or a cell (mobile telephones, cameras, portable computers, etc.).

    摘要翻译： 本发明涉及能够以活动模式或待机模式操作并且在待机模式下具有非常低的电流消耗的电子集成电路。 根据本发明，串联插入在电源端子和有源电路之间的功率晶体管的漏电流由栅极反向过电流以下列方式控制：升压电荷泵由输出的脉冲产生栅极偏置电压 通过其频率由电流控制的振荡器。 控制电流Ic是具有与功率晶体管类似的技术特性的晶体管的漏电流。 该系统优化待机模式下的电流消耗，当栅极偏置时，振荡器的频率降低，从而最小化漏电流。 本发明适用于由电池或电池（移动电话，照相机，便携式计算机等）供电的电路。