公开(公告)号：US07005725B2

公开(公告)日：2006-02-28

申请号：US10744407

申请日：2003-12-23

Applicant: Patrick Poveda

Inventor： Patrick Poveda

IPC: H01L31/105

CPC classification number: H01L21/84 ,  H01L27/0814 ,  H01L27/1203

Abstract: An electric component comprising an assembly of two PIN diodes in series formed in a semiconductor substrate layer separated from a support layer by an insulating layer, the doped areas forming the electrodes of each diode having a depth equal to that of the substrate layer, the component including a first area of a first doping type surrounded with a second intrinsic area, itself surrounded with a third area of a second doping type, the third area being surrounded with a fourth area of the first doping type, the fourth area being surrounded with a fifth intrinsic area, itself surrounded with a sixth area of the second doping type, the third and fourth areas being covered and connected by a metal area, each of the first and sixth areas being connected to a contact pad on which rests a welding ball.

Abstract translation: 一种电气部件，包括串联形成在通过绝缘层从支撑层分离的半导体衬底层中的两个PIN二极管的组件，所述掺杂区域形成具有与衬底层的深度相等的深度的每个二极管的电极，所述部件 包括用第二固有区域包围的第一掺杂类型的第一区域，其本身被第二掺杂类型的第三区域包围，第三区域被第一掺杂类型的第四区域包围，第四区域被 第五本征区域本身被第二掺杂类型的第六区域包围，第三和第四区域被金属区域覆盖并连接，第一和第六区域中的每一个连接到接触焊盘，其上搁置焊接球。

公开(公告)号：US20080158090A1

公开(公告)日：2008-07-03

申请号：US12035458

申请日：2008-02-22

Applicant: Francois Dupont ,  Patrick Poveda

Inventor： Francois Dupont ,  Patrick Poveda

IPC: H01Q1/50 ,  H03H11/04

CPC classification number: H03H7/487

Abstract: A non-directional coupler including a semiconductor junction in series with a capacitor, the semiconductor junction being formed so that the threshold frequency short of which it behaves as a rectifier is smaller than the coupler's operating frequency.

Abstract translation: 包括与电容器串联的半导体结的非定向耦合器，形成半导体结，使得其作为整流器行为的阈值频率小于耦合器的工作频率。

公开(公告)号：US06979852B2

公开(公告)日：2005-12-27

申请号：US10669107

申请日：2003-09-23

Applicant: Patrick Poveda

Inventor： Patrick Poveda

IPC: H01L29/93 ,  H01L29/94 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L29/93 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/94 ,  H01L29/945

Abstract: A variable capacitance formed in a semiconductor substrate with a ribbed surface, having a first electrode formed of all the ribs protruding from the substrate, of portions of the substrate underlying the ribs, and of at least portions of the substrate separating the bases of two ribs, having a second electrode superposed to at least one portion of the first electrode. The ribs are irregular in terms of cross-section and/or planar base surface area.

Abstract translation: 形成在具有肋状表面的半导体衬底中的可变电容器，具有由从衬底突出的所有肋形成的第一电极，位于肋下方的衬底的部分以及分隔两个肋的基部的至少部分的衬底 具有与第一电极的至少一部分重叠的第二电极。 肋在横截面和/或平面基面积方面是不规则的。

公开(公告)号：US06972240B2

公开(公告)日：2005-12-06

申请号：US10717286

申请日：2003-11-19

Applicant: Patrick Poveda

Inventor： Patrick Poveda

IPC: H01L21/308 ,  H01L21/334 ,  H01L21/762 ,  H01L21/76

CPC classification number: H01L29/66181 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76229

Abstract: A method for forming narrow trenches in a silicon substrate, comprising the steps of: etching the substrate to form first trenches separated by first silicon ribs; performing a thermal oxidation of the substrate to form a silicon oxide layer around the substrate, to obtain second trenches and second silicon ribs; filling the second trenches with fingers of an etchable material; etching the oxide down to the upper surface of the second ribs while keeping oxide portions between said material fingers and the second ribs; etching away the second silicon ribs and said material fingers; etching the oxide to expose the substrate at the bottom of the oxide portions, while keeping oxide fingers; and etching the substrate between the oxide fingers to form narrow trenches in the substrate.

Abstract translation: 一种用于在硅衬底中形成窄沟槽的方法，包括以下步骤：蚀刻衬底以形成由第一硅肋分隔开的第一沟槽; 进行基板的热氧化以在基板周围形成氧化硅层，以获得第二沟槽和第二硅肋; 用可蚀刻材料的手指填充第二沟槽; 将氧化物蚀刻到第二肋的上表面，同时保持所述材料指和第二肋之间的氧化物部分; 蚀刻掉第二硅肋和所述材料指; 蚀刻氧化物以在氧化物部分的底部露出衬底，同时保持氧化物指; 并蚀刻氧化物指状物之间的衬底以在衬底中形成窄沟槽。

公开(公告)号：US07760155B2

公开(公告)日：2010-07-20

申请号：US12035458

申请日：2008-02-22

Applicant: François Dupont ,  Patrick Poveda

Inventor： François Dupont ,  Patrick Poveda

IPC: H01Q1/50 ,  H01P5/00

CPC classification number: H03H7/487

Abstract: A non-directional coupler including a semiconductor junction in series with a capacitor, the semiconductor junction being formed so that the threshold frequency short of which it behaves as a rectifier is smaller than the coupler's operating frequency.

Abstract translation: 包括与电容器串联的半导体结的非定向耦合器，形成半导体结，使得其作为整流器行为的阈值频率小于耦合器的工作频率。

公开(公告)号：US07507620B2

公开(公告)日：2009-03-24

申请号：US11159991

申请日：2005-06-23

Applicant: Emmanuel Collard ,  Patrick Poveda

Inventor： Emmanuel Collard ,  Patrick Poveda

IPC: H01L21/8234

CPC classification number: H01L29/868 ,  H01L29/8613

Abstract: A vertical diode of low capacitance formed in a front surface of a semiconductor substrate, including a first area protruding from the substrate surface including at least one doped semiconductor layer of a conductivity type opposite to that of the substrate, the upper surface of the semiconductor layer supporting a first welding ball. The diode includes a second area including on the substrate a thick conductive track supporting at least two second welding balls, said first and second welding balls defining a plane parallel to the substrate plane.

Abstract translation: 一种低电容的垂直二极管，其形成在半导体衬底的前表面中，包括从衬底表面突出的第一区域，该第一区域包括至少一个与衬底相反的导电类型的掺杂半导体层，半导体层的上表面 支持第一焊球。 二极管包括第二区域，该第二区域包括在基板上的支撑至少两个第二焊球的厚导电轨道，所述第一焊球和第二焊球限定平行于衬底平面的平面。

公开(公告)号：US07375603B2

公开(公告)日：2008-05-20

申请号：US10949941

申请日：2004-09-24

Applicant: François Dupont ,  Patrick Poveda

Inventor： François Dupont ,  Patrick Poveda

IPC: H01P5/00 ,  H01P1/20

CPC classification number: H03H7/487

Abstract: A non-directional coupler including a semiconductor junction in series with a capacitor, the semiconductor junction being formed so that the threshold frequency short of which it behaves as a rectifier is smaller than the coupler's operating frequency.

Abstract translation: 包括与电容器串联的半导体结的非定向耦合器，形成半导体结，使得其作为整流器行为的阈值频率小于耦合器的工作频率。

公开(公告)号：US20070018753A1

公开(公告)日：2007-01-25

申请号：US11490740

申请日：2006-07-21

Applicant: Patrick Poveda ,  Francois Dupont

Inventor： Patrick Poveda ,  Francois Dupont

IPC: H01P1/15

CPC classification number: H04B1/005 ,  H04B1/406 ,  H04B1/48

Abstract: An antenna switch module between several radio-frequency transmit and/or receive paths including, between a common terminal on the antenna side and an access capacitor specific to each path, at least one diode, the number of diodes directly connected to the common terminal being odd and the number of diodes having their cathode on the common terminal side being equal, with a difference of one, to the number of diodes having their anode on the common terminal side.

Abstract translation: 在几个射频发射和/或接收路径之间的天线切换模块，包括在天线侧的公共终端和每个路径专用的接入电容器之间，至少一个二极管，直接连接到公共端子的二极管的数量为 奇数，在公共端子侧具有阴极的二极管的数量与公共端子侧的具有阳极的二极管的数量相差1。

公开(公告)号：US20050136613A1

公开(公告)日：2005-06-23

申请号：US11014608

申请日：2004-12-16

Applicant: Patrick Poveda

Inventor： Patrick Poveda

IPC: H01L21/329 ,  H01L29/06 ,  H01L29/40 ,  H01L29/872 ,  H01L21/76

CPC classification number: H01L29/402 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/806 ,  H01L29/872 ,  H01L29/8725

Abstract: A method for forming a component of TMBS type having its periphery formed of a trench with insulated walls filled with a conductor, including the steps of depositing on a semiconductor substrate a thick layer of a first insulating material and a thin layer of a second material; simultaneously digging a peripheral trench and the trenches of the component; isotropically etching the first material so that a cap overhanging a recess remains; forming a thin insulating layer; and filling the trenches and said recess with a conductive material.

Abstract translation: 一种用于形成其外围由填充有导体的绝缘壁形成沟槽的TMBS型的部件的方法，包括以下步骤：在半导体衬底上沉积厚层的第一绝缘材料和第二材料的薄层; 同时挖掘周边沟槽和部件的沟槽; 各向同性蚀刻第一材料，使得悬挂在凹部上的盖保留; 形成薄的绝缘层; 并用导电材料填充沟槽和凹槽。