公开(公告)号：US07702925B2

公开(公告)日：2010-04-20

申请号：US11803051

申请日：2007-05-11

申请人： J. Duane Northcutt ,  Seung Ho Hwang ,  James D. Lyle ,  James G. Hanko

发明人： J. Duane Northcutt ,  Seung Ho Hwang ,  James D. Lyle ,  James G. Hanko

IPC分类号： G06F21/00

CPC分类号： H04L25/03159 ,  H04L63/04 ,  H04L63/166 ,  H04L2025/03356 ,  H04L2025/03522

摘要： In some embodiments, the invention is a personal digital network (“PDN”) including hardware (sometimes referred to as Ingress circuitry) configured to transcrypt encrypted content that enters the PDN. Typically, the transcryption (decryption followed by re-encryption) is performed in hardware within the Ingress circuitry and the re-encryption occurs before the decrypted content is accessible by hardware or software external to the Ingress circuitry. Typically, transcrypted content that leaves the Ingress circuitry remains in re-encrypted form within the PDN whenever it is transferred between integrated circuits or is otherwise easily accessible by software, until it is decrypted within hardware (sometimes referred to as Egress circuitry) for display or playback or output from the PDN. Typically, the PDN is implemented so that no secret in Ingress or Egress circuitry (for use or transfer by the Ingress or Egress circuitry) is accessible in unencrypted form to software or firmware within the PDN or to any entity external to the PDN. Other aspects of the invention are methods for protecting content in a PDN (e.g., an open computing system) and devices (e.g., multimedia graphics cards, set top boxes, or video processors) for use in a PDN.

摘要翻译： 在一些实施例中，本发明是一种个人数字网络（“PDN”），其包括配置成对进入PDN的加密内容进行加密的硬件（有时称为入口电路）。 通常，在入口电路内的硬件中执行转录（后续是重新加密的解密），并且在加密内容可以通过入口电路外部的硬件或软件访问之前发生重新加密。 通常，离开入口电路的加密内容在PDN之间保持重新加密的形式，无论其在集成电路之间传输还是由软件容易地访问，直到在硬件（有时称为出口电路）中被解密以进行显示或 从PDN播放或输出。 通常，PDN被实现为使得入口或出口电路（用于入口或出口电路的使用或传输）中的秘密可以以未加密的形式被访问到PDN内的软件或固件或PDN外部的任何实体。 本发明的其他方面是用于保护PDN（例如，开放式计算系统）中的内容和用于PDN中的设备（例如，多媒体图形卡，机顶盒或视频处理器）的方法。

公开(公告)号：US06870930B1

公开(公告)日：2005-03-22

申请号：US09579811

申请日：2000-05-26

申请人： Gyudong Kim ,  Victor M. Da Costa ,  Bruce Kim ,  David D. Lee ,  Russel A. Martin ,  Seung Ho Hwang

发明人： Gyudong Kim ,  Victor M. Da Costa ,  Bruce Kim ,  David D. Lee ,  Russel A. Martin ,  Seung Ho Hwang

IPC分类号： H04L9/08 ,  H04L9/12 ,  H04L9/18 ,  H04N7/167 ,  H04N7/173 ,  H04L9/00 ,  H04K1/06

CPC分类号： G09G5/006 ,  H04L9/065 ,  H04L9/0844 ,  H04L9/12 ,  H04L2209/046 ,  H04L2209/34 ,  H04L2209/605 ,  H04N7/1675 ,  H04N7/17318 ,  H04N21/23476 ,  H04N21/44055 ,  H04N21/63345

摘要： The present invention is directed to systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of: a) performing transition controlled encoding of a first sequence of n bit data words into encoded n+1 bit data characters where the n is a positive integer, b) performing XOR masking of the encoded n+1 bit data characters with an XOR mask to produce masked n+1 bit data characters; c) DC balancing the masked n+1 bit data characters to produce DC balanced, masked n+2 bit data characters; d) scrambling the DC balanced, masked n+2 bit data characters using a scrambling formula to produce encrypted n+2 bit data characters; e) encoding control data into encoded n+2 bit control characters, f) generating a serial data stream in response to the encrypted data characters and encoded control characters, and g) transmitting the serial data stream over a communication link. Subsequent to step (e) and prior to step (f), the method can further include the step of encrypting the encoded n+2 bit control characters, such that the generating step generates a serial data stream in response to the encrypted data characters and the encrypted control characters.

摘要翻译： 本发明涉及用于在传输期间保护数字内容的系统和方法。 本发明的一个方案提供了一种用于在高速数字视频传输系统中进行加密的方法，该方法包括以下步骤：a）对n位数据字的第一序列进行转换控制编码，以编码到编码的n + 1位数据字符中，其中 n是正整数，b）用XOR掩码执行编码的n + 1位数据字符的异或掩蔽，以产生掩蔽的n + 1位数据字符; c）直流平衡屏蔽的n + 1位数据字符，以产生直流平衡，屏蔽的n + 2位数据字符; d）使用扰频公式对DC平衡掩蔽的n + 2位数据字符进行加扰，以产生加密的n + 2位数据字符; e）将控制数据编码为编码的n + 2位控制字符，f）响应于加密的数据字符和编码的控制字符产生串行数据流，以及g）通过通信链路发送串行数据流。 在步骤（e）之后和步骤（f）之后，该方法还可以包括对编码的n + 2位控制字符进行加密的步骤，使得生成步骤响应于加密的数据字符生成串行数据流，并且 加密的控制字符。

公开(公告)号：US06625560B1

公开(公告)日：2003-09-23

申请号：US09904783

申请日：2001-07-13

申请人： Ziaus S. Molla ,  Victor DaCosta ,  Seung Ho Hwang ,  Baegin Sung

发明人： Ziaus S. Molla ,  Victor DaCosta ,  Seung Ho Hwang ,  Baegin Sung

IPC分类号： G06F1100

CPC分类号： G01R31/31709 ,  G01R31/31922 ,  G01R31/31937

摘要： A method of testing a circuit having an interface which includes data and clock information where phase jitter is introduced into the clock that produces the clock information. The clock is cycled by increasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift advance in the clock. The clock is also cycled by decreasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift delay in the clock. The circuit under test is caused to sample the data using a clock derived from the clock information. The sampled data is then compared with reference data to determine the error rate.

摘要翻译： 一种测试具有接口的电路的方法，该接口包括将相位抖动引入产生时钟信息的时钟中的数据和时钟信息。 通过将时钟周期增加预定数量的时钟周期来循环时钟，以便在时钟中引入递增的相移提前。 时钟也通过在预定数量的时钟周期内减小时钟周期来循环，以便在时钟中引入增加的相移延迟。 使用由时钟信息导出的时钟对被测电路进行采样。 然后将采样数据与参考数据进行比较以确定错误率。

公开(公告)号：US07158593B2

公开(公告)日：2007-01-02

申请号：US10099533

申请日：2002-03-15

申请人： Gyudong Kim ,  Ook Kim ,  Min-Kyu Kim ,  Bruce Kim ,  Seung Ho Hwang

发明人： Gyudong Kim ,  Ook Kim ,  Min-Kyu Kim ,  Bruce Kim ,  Seung Ho Hwang

IPC分类号： H04L7/00

CPC分类号： H04L25/4902 ,  G09G5/006 ,  H04L5/06 ,  H04L7/0008 ,  H04L7/0054 ,  H04L7/027

摘要： A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.

摘要翻译： 公开了一种在包括至少一个数据信道和单独的时钟信道的系统中发送数据的方法。 该方法包括将要在时钟信道上发送的时钟信号与数据信号组合以产生组合的时钟和数据信号。 在一个实施例中，数据信号已经使用使数据信号的能谱偏离时钟信号的能谱的编码方案从数据字生成。 在另一个实施例中，时钟信号具有多个脉冲，每个脉冲具有前沿和后沿，并且数据信号通过移动多个脉冲的至少一个边缘（即，前面或背面或两者）被调制到时钟信号上 脉冲，从而创建一个组合的时钟和数据信号。

公开(公告)号：US07079579B2

公开(公告)日：2006-07-18

申请号：US09905096

申请日：2001-07-13

申请人： Tae-Hee Han ,  Seung Ho Hwang

发明人： Tae-Hee Han ,  Seung Ho Hwang

IPC分类号： H04N7/18

CPC分类号： H04N19/57 ,  H04N19/43 ,  H04N19/433 ,  H04N19/51

摘要： There is provided a block matching processor and method for flexibly supporting block matching motion estimation at motion vector prediction modes using matching blocks of various sizes. Each of difference unit (D-unit) arrays takes each smallest size matching block, calculates the difference between the pixels of a current frame and the pixels of a reference frame, and converts the differences to absolute values. An accumulator generates SADs (Sum of Absolute Difference) for the smallest size matching blocks and SADs for all the matching blocks of various sizes by tree-like hierarchical addition of the absolute values of the smallest size matching blocks received from the D-unit arrays.

公开(公告)号：US07236553B1

公开(公告)日：2007-06-26

申请号：US10763905

申请日：2004-01-23

申请人： Hoon Choi ,  Gyudong Kim ,  Daeyun Shim ,  Bruce Kim ,  Seung Ho Hwang

发明人： Hoon Choi ,  Gyudong Kim ,  Daeyun Shim ,  Bruce Kim ,  Seung Ho Hwang

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H04L7/0008

摘要： A data sampling method and circuit employing an oversampling clock to oversample a data signal, a phase tracker for use with or in a data sampling circuit, and a method for identifying a sequence of best sampling positions for sampling a data signal from signal samples generated using an oversampling clock. In some embodiments, data indicative of the phase of at least one of the oversampling clock's sampling positions relative to the center of the data eye are low-pass filtered in a manner determined by the data signal's bit rate. In other embodiments, the number of dead cycles of the phase tracker decision loop is reduced by generating possible solutions in parallel and moving the feedback point so as to occur as late as practical, or the phase tracker ignores a sample set when updating its determination of the best sampling position when the sample set indicates that the data signal has less than a predetermined number of transitions during a corresponding tracking period.

摘要翻译： 使用过采样时钟对数据信号进行过采样的数据采样方法和电路，与数据采样电路一起使用或在数据采样电路中使用的相位跟踪器，以及用于识别最佳采样位置序列的方法，用于从使用 过采样时钟。 在一些实施例中，指示相对于数据眼睛的中心的过采样时钟的采样位置中的至少一个的相位的数据以由数据信号的比特率确定的方式进行低通滤波。 在其他实施例中，相位跟踪器判定循环的死循环的数量通过并行产生可能的解并且将反馈点移动以便尽可能晚地发生而减少，或者当更新其样本集的确定时，相位跟踪器忽略样本集 当样本集合表示在对应的跟踪周期期间数据信号具有小于预定数量的转换时的最佳采样位置。

公开(公告)号：US06463092B1

公开(公告)日：2002-10-08

申请号：US09393235

申请日：1999-09-09

申请人： Gyudong Kim ,  Min-Kyu Kim ,  Seung Ho Hwang

发明人： Gyudong Kim ,  Min-Kyu Kim ,  Seung Ho Hwang

IPC分类号： H04B138

CPC分类号： G09G5/006 ,  G09G5/008 ,  G09G2370/04 ,  H04L7/0008 ,  H04L25/4902

摘要： The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.

摘要翻译： 该系统优选地包括在同一传输线上发送时钟和数据信号的唯一发射机。 接收机使用相同的传输线将数据信号发送回发射机。 发射机包括时钟发生器，解码器和线路接口。 时钟发生器产生包括可变位置下降沿的时钟信号。 下降沿位置被接收器解码以从时钟信号中提取数据。 接收机包括时钟再生器，数据解码器和返回通道编码器。 时钟再发生器监视传输线，接收信号，对它们进行滤波，并在接收机上根据传输线上的信号产生时钟信号。 返回通道编码器产生信号并在传输线上断言它们。 该信号被断言或叠加在发射机提供的时钟和数据信号上。