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    System and method for generating fix-up code facilitating avoidance of an exception of a predetermined type in a digital computer system
    12.
    发明授权
    System and method for generating fix-up code facilitating avoidance of an exception of a predetermined type in a digital computer system 有权
    用于产生修复代码的系统和方法，其有助于避免数字计算机系统中的预定类型的异常

    公开(公告)号：US6064815A

    公开(公告)日：2000-05-16

    申请号：US207476

    申请日：1998-12-08

    申请人： Paul H. Hohensee ,  David L. Reese

    发明人： Paul H. Hohensee ,  David L. Reese

    IPC分类号： G06F9/455 ,  G06F9/38 ,  G06F9/44

    CPC分类号： G06F9/3861

    摘要： A system for avoiding exceptional conditions during execution of a program comprises an execution enviornment for executing the program and a fix-up code generation subsystem. The program comprises an instruction stream comprising a series of instructions, and the execution environment includes an exceptional condition detector for detecting at least one predetermined type of exceptional condition in connection with execution of each instruction in the instruction stream. The fix-up code generation subsystem is responsive to detection by the execution environment of an exceptional condition of the predetermined type in connection with execution of an instruction in the instruction stream for generating fix-up code which, when processed, would avoid the exceptional condition of that predetermined type, and substitutes the fix-up code in the instruction stream for the instruction in the instruction stream for which the at least one exceptional condition was detected. As a result, if the instruction which gave rise to the exception is in a loop or the like, instead of the instruction being processed, the fix-up code will be processed, which will avoid the exception condition.

    摘要翻译： 用于在执行程序期间避免异常情况的系统包括用于执行程序的执行环境和修复代码生成子系统。 该程序包括包括一系列指令的指令流，并且执行环境包括例外条件检测器，用于与指令流中的每个指令的执行相关联地检测至少一种预定类型的异常条件。 固定代码生成子系统响应于执行环境检测与指令流中的指令的执行相关联的预定类型的异常情况，用于产生修正代码，该修正代码在被处理时将避免例外情况 并且将指令流中的修正代码替换为检测到至少一个异常条件的指令流中的指令。 结果，如果引起异常的指令处于循环等中，则代替正在处理的指令，将处理修正代码，这将避免异常情况。

    Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions
    13.
    发明授权
    Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions 有权
    检测从一台计算机指令流传输到另一台计算机指令流的条件，并在满足条件的情况下执行转移

    公开(公告)号：US08121828B2

    公开(公告)日：2012-02-21

    申请号：US11003768

    申请日：2004-12-02

    申请人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell ,  Korbin S. Van Dyke

    发明人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell ,  Korbin S. Van Dyke

    IPC分类号： G06F9/455

    CPC分类号： G06F9/45533

    摘要： A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

    摘要翻译： 计算机具有能够执行两个指令集架构（ISA）的指令流水线电路。 二进制翻译器至少将计算机程序的选定部分从ISA的较低性能转换为ISA的更高性能的一个。 当即将执行在低性能ISA中编码的程序区域时，硬件启动查询，以确定是否存在更高性能的转换。 如果是这样，即将执行的指令被中止，并且控制转移到更高性能的转换。 执行较高性能的翻译后，在排除后的指令下游的一个点重新建立较低性能区域的执行，在逻辑上相当于在较低性能区域的代码被允许的情况下 继续。

    Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor
    14.
    发明授权
    Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor 有权
    使用由指令地址索引的片上和片外查找表来控制处理器中的指令执行

    公开(公告)号：US08065504B2

    公开(公告)日：2011-11-22

    申请号：US11004729

    申请日：2004-12-02

    申请人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  Shalesh Thusoo ,  Tiruvur R. Ramesh

    发明人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  Shalesh Thusoo ,  Tiruvur R. Ramesh

    IPC分类号： G06F9/30

    CPC分类号： G06F9/45533

    摘要： A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.

    摘要翻译： 微处理器芯片具有指令流水线电路和指令分类电路，它们将执行的指令分类为少量类并记录分类代码值。 片上表具有对应于存储器的一系列地址的条目，并且被设计为保持在计算机的存储器中查看片外表的值的统计评估。 查找电路被设计为从微处理器的基本指令处理周期的一部分获取片上表格中的条目。 掩码至少部分由定时器设置的值。 基于与所处理的指令的地址，掩码的当前值，记录的分类代码和片外表相对应的片上表项的值来控制指令流水线电路。

    Low-Contention Update Buffer Queuing For Large Systems
    15.
    发明申请
    Low-Contention Update Buffer Queuing For Large Systems 有权
    针对大型系统的低竞争更新缓冲区排队

    公开(公告)号：US20110191508A1

    公开(公告)日：2011-08-04

    申请号：US12699370

    申请日：2010-02-03

    申请人： Antonios Printezis ,  Paul H. Hohensee

    发明人： Antonios Printezis ,  Paul H. Hohensee

    IPC分类号： G06F13/00 ,  G06F9/46 ,  G06F9/455

    CPC分类号： G06F12/0253 ,  G06F5/12 ,  G06F9/455 ,  G06F9/46 ,  G06F13/00

    摘要： A method for queuing thread update buffers to enhance garbage collection. The method includes providing a global update buffer queue and a global array with slots for storing pointers to filled update buffers. The method includes with an application thread writing to the update buffer and, when filled, attempting to write the pointer for the update buffer to the global array. The array slot may be selected randomly or by use of a hash function. When the writing fails due to a non-null slot, the method includes operating the application thread to add the filled update buffer to the global update buffer queue. The method includes, with a garbage collector thread, inspecting the global array for non-null entries and, upon locating a pointer, claiming the filled update buffer. The method includes using the garbage collector thread to claim and process buffers added to the global update buffer queue.

    摘要翻译： 排队线程更新缓冲区以增强垃圾回收的方法。 该方法包括提供全局更新缓冲器队列和全局阵列，其具有用于存储指向填充的更新缓冲器的指针的时隙。 该方法包括应用程序线程写入更新缓冲区，并在填充时尝试将更新缓冲区的指针写入全局数组。 可以随机地或通过使用散列函数来选择阵列时隙。 当由于非空插槽而导致写入失败时，该方法包括操作应用程序线程以将填充的更新缓冲区添加到全局更新缓冲区队列。 该方法包括：使用垃圾收集器线程，检查全局数组的非空条目，并在找到指针时声明填充的更新缓冲区。 该方法包括使用垃圾收集器线程来声明和处理添加到全局更新缓冲区队列中的缓冲区。

    Safety net paradigm for managing two computer execution modes
    17.
    发明授权
    Safety net paradigm for managing two computer execution modes 有权
    用于管理两台计算机执行模式的安全网范例

    公开(公告)号：US06789181B1

    公开(公告)日：2004-09-07

    申请号：US09432753

    申请日：1999-11-03

    申请人： John S. Yates ,  David L. Reese ,  Korbin S. Van Dyke ,  Paul H. Hohensee

    发明人： John S. Yates ,  David L. Reese ,  Korbin S. Van Dyke ,  Paul H. Hohensee

    IPC分类号： G06F944

    CPC分类号： G06F9/45533

    摘要： A method and computer for executing the method. A source program is translated into an object program, in a manner in which the translated object program has a different execution behavior than the source program. The translated object program is executed under a monitor capable of detecting any deviation from fully-correct interpretation before any side-effect of the different execution behavior is irreversibly committed. When the monitor detects the deviation, or when an interrupt occurs during execution of the object program, a state of the program is established corresponding to a state that would have occurred during an execution of the source program, and from which execution can continue. Execution of the source program continues primarily in a hardware emulator designed to execute instructions of an instruction set non-native to the computer.

    摘要翻译： 一种用于执行该方法的方法和计算机。 源程序被翻译成对象程序，其中翻译的对象程序具有与源程序不同的执行行为。 在不可执行行为的任何副作用被不可逆转地提交之前，被翻译的对象程序在能够检测到完全正确解释的任何偏离的监视器下执行。 当监视器检测到偏差时，或者在执行对象程序期间发生中断时，根据在源程序执行期间发生的状态并且从哪个执行继续可以建立程序的状态。 源程序的执行主要在硬件仿真器中进行，该硬件仿真器旨在执行非本机的指令集的指令。

    System and method for facilitating avoidance of an exception of a predetermined type in a digital computer system by providing fix-up code for an instruction in response to detection of an exception condition resulting from execution thereof
    18.
    发明授权
    System and method for facilitating avoidance of an exception of a predetermined type in a digital computer system by providing fix-up code for an instruction in response to detection of an exception condition resulting from execution thereof 失效
    用于在数字计算机系统中避免预定类型的异常的系统和方法，通过提供响应于由执行引起的异常状况的检测的指令的固定代码

    公开(公告)号：US5907708A

    公开(公告)日：1999-05-25

    申请号：US657112

    申请日：1996-06-03

    申请人： Paul H. Hohensee ,  David L. Reese

    发明人： Paul H. Hohensee ,  David L. Reese

    IPC分类号： G06F9/455 ,  G06F9/38 ,  G06F9/44

    CPC分类号： G06F9/3861

    摘要： A system for avoiding exceptional conditions during execution of a program comprises an execution environment for executing the program and a fix-up code generation subsystem. The program comprises an instruction stream comprising a series of instructions, and the execution environment includes an exceptional condition detector for detecting at least one predetermined type of exceptional condition in connection with execution of each instruction in the instruction stream. The fix-up code generation subsystem is responsive to detection by the execution environment of an exceptional condition of the predetermined type in connection with execution of an instruction in the instruction stream for generating fix-up code which, when processed, would avoid the exceptional condition of that predetermined type, and substitutes the fix-up code in the instruction stream for the instruction in the instruction stream for which the at least one exceptional condition was detected. As a result, if the instruction which gave rise to the exception is in a loop or the like, instead of the instruction being processed, the fix-up code will be processed, which will avoid the exception condition.

    摘要翻译： 用于在执行程序期间避免异常情况的系统包括用于执行程序的执行环境和修补代码生成子系统。 该程序包括包括一系列指令的指令流，并且执行环境包括例外条件检测器，用于与指令流中的每个指令的执行相关联地检测至少一种预定类型的异常条件。 固定代码生成子系统响应于执行环境检测与指令流中的指令的执行相关联的预定类型的异常情况，用于产生修正代码，该修正代码在被处理时将避免例外情况 并且将指令流中的修正代码替换为检测到至少一个异常条件的指令流中的指令。 结果，如果引起异常的指令处于循环等中，则代替正在处理的指令，将处理修正代码，这将避免异常情况。

    Technologies for native code invocation using binary analysis
    19.
    发明申请
    Technologies for native code invocation using binary analysis 有权

    公开(公告)号：US20170185386A1

    公开(公告)日：2017-06-29

    申请号：US14998274

    申请日：2015-12-26

    申请人： Abhay S. Kanhere ,  Haitao Feng ,  Paul H. Hohensee ,  Aravind Subramanian

    发明人： Abhay S. Kanhere ,  Haitao Feng ,  Paul H. Hohensee ,  Aravind Subramanian

    IPC分类号： G06F9/45

    CPC分类号： G06F8/433 ,  G06F8/53

    摘要： Technologies for native code invocation using binary analysis are described. A computing device for invoking native code from managed code using binary analysis receives a call from a thread executing a managed code segment to execute a native code segment. The computing device performs a binary analysis of the native code segment and generates, from the binary analysis, a complexity indicator that indicates a level of complexity of the native code segment by comparing the native code segment to at least one predefined complexity rule. Additionally, the computing device stores a status of the thread based on the complexity indicator and executes the native code segment. Other embodiments are described and claimed.

    Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
    20.
    发明授权
    Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code 有权
    当执行从第一架构代码流向第二架构代码时，更改处理器的数据存储约定

    公开(公告)号：US08074055B1

    公开(公告)日：2011-12-06

    申请号：US09385394

    申请日：1999-08-30

    申请人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke ,  Tiruvur R. Ramesh ,  Paul H. Hohensee

    发明人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke ,  Tiruvur R. Ramesh ,  Paul H. Hohensee

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3005 ,  G06F9/30174 ,  G06F9/3804

    摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.

    摘要翻译： 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线将来自第一页面的执行流程（其相关联的指示符元素指示第一架构或执行约定）识别到第二页面，其第二页面的相关联的指示符元素指示第一个架构或执行约定。 响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。