公开(公告)号：US06978462B1

公开(公告)日：2005-12-20

申请号：US09332263

申请日：1999-06-11

申请人： Michael C. Adler ,  John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell

发明人： Michael C. Adler ,  John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell

IPC分类号： G06F3/00

CPC分类号： G06F11/348 ,  G06F9/30149 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3851

摘要： A computer having an instruction pipeline and profile circuitry. The profile circuitry detects and records, without compiler assistance for execution profiling, profile information describing a sequence of events occurring in the instruction pipeline. The sequence includes every event occurring during a profiled execution interval that matches time-independent selection criteria of events to be profiled. The recording continues until a predetermined stop condition is reached. The profile circuitry detects the occurrence of a predetermined condition, after a non-profiled interval of execution, and then commences the profiled execution interval.

摘要翻译： 具有指令流水线和简档电路的计算机。 简档电路检测和记录，无需编译器协助执行分析，描述描述在指令流水线中发生的事件序列的简档信息。 该序列包括在分析执行间隔期间发生的每个事件，其与要分析的事件的时间无关的选择标准相匹配。 记录继续，直到达到预定的停止条件。 配置文件电路在非分析执行间隔之后检测预定条件的发生，然后开始分析执行间隔。

公开(公告)号：US07013456B1

公开(公告)日：2006-03-14

申请号：US09334530

申请日：1999-06-16

申请人： Korbin S. Van Dyke ,  Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Stephen C. Purcell ,  Niteen Aravind Patkar

发明人： Korbin S. Van Dyke ,  Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Stephen C. Purcell ,  Niteen Aravind Patkar

IPC分类号： G06F9/44

CPC分类号： G06F9/45533 ,  G06F9/45541 ,  G06F9/45554

摘要： A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.

摘要翻译： 一种用于执行该方法的方法和计算机。 在计算机上执行程序时，检测到在指令流水线中发生的可轮廓事件。 该指令流水线用于记录描述可概要事件的简档信息，基本上与可概要事件的发生同时发生。 检测和记录在没有软件干预的情况下在计算机硬件的控制下进行。

公开(公告)号：US06763452B1

公开(公告)日：2004-07-13

申请号：US09339797

申请日：1999-06-24

申请人： Paul H. Hohensee ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  David L. Reese ,  Stephen C. Purcell

发明人： Paul H. Hohensee ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  David L. Reese ,  Stephen C. Purcell

IPC分类号： G06F900

CPC分类号： G06F9/45558 ,  G06F9/45541 ,  G06F9/45554 ,  G06F2009/45583

摘要： A method and a multiprocessor computer for execution of the method. A first CPU has a general register file, an instruciton pipeline, and profile circuitry. The profile circuitry is operatively interconnected and under common hardware control with the instruction pipeline. The profile circuitry and instruction pipeline are cooperatively interconnected to detect the occurrence of profileable events occurring in the instruction pipeline. The profile circuitry is operable without software intervention to effect recording of profile information describing the profileable events into the general register file, without first capturing the information into a main memory of the computer. The recording is essentially concurrent with the occurrence of the profileable events. A second CPU is configured to analyze the generated profile data, while the execution and profile data generation continue on the first CPU, and to control the execution of the program on the first CPU based at least in part on the analysis of the collected profile data.

摘要翻译： 一种用于执行该方法的方法和多处理器计算机。 第一个CPU有一个通用寄存器文件，一个通道管道和一个轮廓电路。 配置文件电路与指令管道可操作地互连，并在通用的硬件控制下。 配置文件电路和指令流水线协同互连，以检测在指令流水线中发生的可轮廓事件的发生。 配置文件电路可操作而无需软件干预，以便将描述可描述事件的简档信息记录到通用寄存器文件中，而无需首先将信息捕获到计算机的主存储器中。 录音本质上与可配置事件的发生同时发生。 第二CPU被配置为分析生成的简档数据，同时在第一CPU上继续执行和简档数据生成，并且至少部分地基于所收集的简档数据的分析来控制第一CPU上的程序的执行 。

公开(公告)号：US08121828B2

公开(公告)日：2012-02-21

申请号：US11003768

申请日：2004-12-02

申请人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell ,  Korbin S. Van Dyke

发明人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell ,  Korbin S. Van Dyke

IPC分类号： G06F9/455

CPC分类号： G06F9/45533

摘要： A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

摘要翻译： 计算机具有能够执行两个指令集架构（ISA）的指令流水线电路。 二进制翻译器至少将计算机程序的选定部分从ISA的较低性能转换为ISA的更高性能的一个。 当即将执行在低性能ISA中编码的程序区域时，硬件启动查询，以确定是否存在更高性能的转换。 如果是这样，即将执行的指令被中止，并且控制转移到更高性能的转换。 执行较高性能的翻译后，在排除后的指令下游的一个点重新建立较低性能区域的执行，在逻辑上相当于在较低性能区域的代码被允许的情况下 继续。

公开(公告)号：US20160296747A1

公开(公告)日：2016-10-13

申请号：US14681036

申请日：2015-04-07

申请人： Richard A. Glenn ,  Stephen C. Purcell

发明人： Richard A. Glenn ,  Stephen C. Purcell

IPC分类号： A61N1/05

CPC分类号： A61N1/0551 ,  A61N1/0558

摘要： An intravascular catheter is positionable within a blood vessel for use in transvenous stimulation of targets external to the wall of the blood vessel. The catheter includes a catheter body, a support at the distal end of the catheter body, and a plurality of electrodes carried by the support. At least a portion of the support being inflatable within the blood vessel to bias at least a portion of the plurality of electrodes into contact with the blood vessel wall.

摘要翻译： 血管内导管可定位在血管内，用于静脉刺激血管壁外的靶。 导管包括导管主体，在导管主体的远端处的支撑件和由支撑件承载的多个电极。 所述支撑体的至少一部分在所述血管内是可充气的，以将所述多个电极的至少一部分偏置成与所述血管壁接触。

公开(公告)号：US20110283293A1

公开(公告)日：2011-11-17

申请号：US13190253

申请日：2011-07-25

申请人： Korbin Van Dyke ,  Paul Campbell ,  Don Van Dyke ,  Ali Alasti ,  Stephen C. Purcell

发明人： Korbin Van Dyke ,  Paul Campbell ,  Don Van Dyke ,  Ali Alasti ,  Stephen C. Purcell

IPC分类号： G06F9/50

CPC分类号： G06F9/5044

摘要： A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

摘要翻译： 一种用于动态分配处理资源和任务的方法和装置，包括多媒体任务。 任务排队，识别可用的处理资源，并在任务之间分配可用的处理资源。 可用的处理资源具有与任务相对应的功能程序。 使用可用的处理资源执行任务以产生结果数据，并将所得到的数据传递到输入/输出设备。

公开(公告)号：US20100122262A1

公开(公告)日：2010-05-13

申请号：US12688562

申请日：2010-01-15

申请人： Korbin Van Dyke ,  Paul Campbell ,  Don Van Dyke ,  Ali Alasti ,  Stephen C. Purcell

发明人： Korbin Van Dyke ,  Paul Campbell ,  Don Van Dyke ,  Ali Alasti ,  Stephen C. Purcell

IPC分类号： G06F9/46

CPC分类号： G06F9/5044

摘要： A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

摘要翻译： 一种用于动态分配处理资源和任务的方法和装置，包括多媒体任务。 任务排队，识别可用的处理资源，并在任务之间分配可用的处理资源。 可用的处理资源具有与任务相对应的功能程序。 使用可用的处理资源执行任务以产生结果数据，并将所得到的数据传递到输入/输出设备。

公开(公告)号：US06449671B1

公开(公告)日：2002-09-10

申请号：US09328971

申请日：1999-06-09

申请人： Niteen A. Patkar ,  Stephen C. Purcell ,  Shalesh Thusoo ,  Korbin S. Van Dyke

发明人： Niteen A. Patkar ,  Stephen C. Purcell ,  Shalesh Thusoo ,  Korbin S. Van Dyke

IPC分类号： G06F1300

CPC分类号： G06F12/0806

摘要： A method and apparatus for busing data elements within a computing system includes processing that begins by providing, on a shared bus, a first control signal relating to a first transaction during a first bus cycle. The processing continues by providing a second control signal relating to a second transaction and a first address signal relating to the first transaction during a second bus cycle. The processing continues by providing a third control signal relating to a third transaction and a second address signal relating to a second transaction during a third bus cycle. The processing then continues by providing a first status relating to the first transaction and a third addressing signal relating to the third transaction during a fourth bus cycle. The processing then continues by providing a second status relating to the second transaction during a fifth bus cycle. The processing then continues by providing first data relating to the first transaction when the first status is a hit and providing third status relating to the third transaction during a sixth bus cycle.

摘要翻译： 用于在计算系统内传送数据元素的方法和装置包括开始于在共享总线上提供在第一总线周期期间与第一事务相关的第一控制信号的处理。 通过在第二总线周期期间提供与第二事务相关的第二控制信号和与第一事务相关的第一地址信号来继续处理。 通过在第三总线周期期间提供与第三事务相关的第三控制信号和与第二事务相关的第二地址信号来继续处理。 然后通过在第四总线周期期间提供与第一事务相关的第一状态和与第三事务相关的第三寻址信号来继续处理。 然后通过在第五总线周期期间提供与第二事务相关的第二状态来继续处理。 然后，当第一状态是命中时，通过提供与第一事务有关的第一数据继续处理，并在第六总线周期期间提供与第三事务有关的第三状态。

公开(公告)号：US06393453B1

公开(公告)日：2002-05-21

申请号：US09159271

申请日：1998-09-22

申请人： Stephen C. Purcell

发明人： Stephen C. Purcell

IPC分类号： G06F738

CPC分类号： G06F7/552 ,  G06F2207/5523

摘要： A circuit for squaring an n-bit value includes a partial product bit generator which logically AND's a bit of the n-bit value having a weight 2k (k is an integer) with the same bit of weight 2k to generate a partial product bit of weight 22k. Another partial product bit generator receives and logically AND's a bit of the n-bit value of weight 2k and a bit of weight 2m (m is an integers) to generate a partial product bit of weight 2(k+m+1). The second partial product bit generator may be the only partial product bit generator in the squaring circuit to logically AND the bit of weight 2m and the bit of weight 2k. The circuit may also include other partial product bit generators. However, the required number of partial product bit generators is significantly reduced by about ½ compared to the conventional squaring circuit. The associated Wallace tree structure is simplified and made smaller because of the reduction in partial product bits. Therefore, a faster and smaller circuit for squaring is provided.

摘要翻译： 用于平方n比特值的电路包括部分乘积比特发生器，逻辑上是与具有相同比特重量2k的权重为2k（k为整数）的n比特值的比特，以产生部分乘积比特 体重22k。 另一个部分产品位发生器接收AND逻辑AND的重量为2k的n位值的位，并且重量为2m（m为整数）的位，以产生权重为2（k + m + 1）的部分乘积位。 第二部分乘积比特发生器可以是平方电路中的唯一的部分乘积比特发生器，用于逻辑上与权重2m的比特和权重2k的比特。 电路还可以包括其他部分产品位发生器。 然而，与常规平方电路相比，所需数量的部分产品位发生器大大减少了约1/2。 由于部分产品位的减少，相关的华莱士树结构被简化并变得更小。 因此，提供了更快更小的平方电路。

公开(公告)号：US6081823A

公开(公告)日：2000-06-27

申请号：US100266

申请日：1998-06-19

申请人： Stephen C. Purcell ,  Nital P. Patwa

发明人： Stephen C. Purcell ,  Nital P. Patwa

IPC分类号： G06F7/52

CPC分类号： G06F7/5338 ,  G06F7/49994

摘要： A multiplier has two input value terminals which receive two signed input bit groups. The multiplier also has two output terminals configured to carry a sum and carry bit group representing, in redundant form, a product of the two signed input values. A sign determining circuit generates a sign bit representing a sign of the product of the two input signed values. An extension unit has three input terminals configured to receive the most significant bit of the sum bit group, the most significant bit of the carry bit group, and the sign bit generated by the sign determining circuit. The extension unit is structure to generate a least significant extension bit and a more significant extension bit. The least significant extension bit has one binary state if the sum most significant bit, the sign bit, and the carry most significant bit have the same binary state. The least significant extension bit otherwise has the opposite binary state.

摘要翻译： 乘法器具有两个输入值端子，其接收两个带符号的输入位组。 乘法器还具有两个输出端子，其被配置为携带以冗余形式表示两个带符号输入值的乘积的和和携带位组。 符号确定电路产生表示两个输入有符号值的积的符号的符号位。 扩展单元具有三个输入端子，其被配置为接收和位组的最高有效位，进位位组的最高有效位以及由符号确定电路产生的符号位。 扩展单元是生成最低有效扩展位和更重要的扩展位的结构。 如果最高有效位，符号位和进位最高有效位具有相同的二进制状态，则最低有效扩展位具有一个二进制状态。 最不重要的扩展位否则具有相反的二进制状态。