公开(公告)号：US07872512B2

公开(公告)日：2011-01-18

申请号：US12060795

申请日：2008-04-01

申请人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

发明人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

IPC分类号： H03K3/289

CPC分类号： H03K3/0375

摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器具有降低的竞争条件的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。

公开(公告)号：US07724031B2

公开(公告)日：2010-05-25

申请号：US11726472

申请日：2007-03-21

申请人： David Cashman

发明人： David Cashman

IPC分类号： H01L25/00 ,  H03K19/177 ,  H03K17/693

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： A staggered logic array block (LAB) architecture can be provided. An integrated circuit (IC) device can include a first group of LABs substantially aligned with each other, and a second group of LABs substantially aligned with each other and coupled to the first group of LABs by a plurality of horizontal and vertical conductors. The first group of LABs can be substantially offset from the second group of LABs in the IC layout. In an embodiment of the invention, the first and second groups of LABs can be columns of LABs, and the columns can be vertically offset from each other (e.g., by half the number of logic elements in each LAB). The offsetting can advantageously allow more LABs to be reached using a single routing channel, or without using any routing channel, thereby reducing communication latency and improving overall IC performance.

摘要翻译： 可以提供交错的逻辑阵列块（LAB）架构。 集成电路（IC）装置可以包括彼此基本对齐的第一组LAB，以及基本上彼此对准并且由多个水平和垂直导体耦合到第一组LAB的第二组LAB。 第一组LAB可以与IC布局中的第二组LAB基本相抵。 在本发明的一个实施例中，第一和第二组LAB可以是LAB的列，并且列可以彼此垂直偏移（例如，每个LAB中的逻辑元件的数量的一半）。 偏移可以有利地允许使用单个路由信道来达到更多的LAB，或者不使用任何路由信道，从而减少通信等待时间并提高总体IC性能。

公开(公告)号：US07619443B1

公开(公告)日：2009-11-17

申请号：US11356762

申请日：2006-02-16

申请人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

发明人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

摘要翻译： 可编程逻辑器件（“PLD”）架构包括被称为逻辑阵列块（LABs“）的集群在一起的逻辑元件（”LE“）。为了保存区域，本地反馈资源（用于将LAB中的LE的输出馈送回到 与现有技术相比，减少或消除了LAB中的LE的输入），因为在LAB中一起工作的LE的任何LE输出到LE输入连接的所有（或至少更多）必须是 通过LAB的通用输入路由资源路由，重要的是保存这些资源，例如，通过更加重视找到具有共同输入的逻辑功能，在决定在 劳顾会

公开(公告)号：US20080218197A1

公开(公告)日：2008-09-11

申请号：US11739055

申请日：2007-04-23

申请人： David Lewis ,  David Cashman

发明人： David Lewis ,  David Cashman

IPC分类号： H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/00392 ,  H03K19/17728

摘要： A PLD having logic element row granularity redundancy is disclosed. The PLD includes a plurality of LABs arranged in an array and a plurality of horizontal and vertical inter-LAB lines interconnecting the LABs of the array. Each of the LABs further includes a predetermined number of logic elements and redundancy circuitry to replace a defective logic element with a non-defective logic element among the predetermined logic elements by shifting programming data intended to for the defective logic element to the non-defective logic element.

摘要翻译： 公开了具有逻辑元件行粒度冗余的PLD。 PLD包括布置在阵列中的多个LAB以及互连阵列的LAB的多个水平和垂直的LAB线。 每个LAB还包括预定数量的逻辑元件和冗余电路，以通过将用于故障逻辑元件的编程数据移位到无缺陷逻辑来在预定逻辑元件中用无缺陷逻辑元件代替故障逻辑元件 元件。

公开(公告)号：US20130257476A1

公开(公告)日：2013-10-03

申请号：US13434847

申请日：2012-03-29

申请人： David Cashman ,  David Lewis ,  Valavan Manohararajah

发明人： David Cashman ,  David Lewis ,  Valavan Manohararajah

IPC分类号： H03K19/20

CPC分类号： H03K19/17728

摘要： A programmable logic region on a programmable integrated circuit may include a first set of look-up tables that receive programmable logic region input signals and a second set of look-up tables that produce programmable logic region output signals. Multiplexer circuitry may be interposed between the first and second sets of look-up tables. The multiplexer circuitry may receive the programmable logic region input signals in parallel with the output signals from the first set of look-up tables and may provide corresponding selected signals to the second set of look-up tables. The programmable logic region input signals may be shared by the first and second sets of look-up tables. Logic circuitry may be coupled to outputs of the first and second sets of look-up tables. The logic circuitry may be configured to logically combine output signals from the first and second sets of look-up tables.

摘要翻译： 可编程集成电路上的可编程逻辑区域可以包括接收可编程逻辑区域输入信号的第一组查询表和产生可编程逻辑区域输出信号的第二组查找表。 多路复用器电路可以插入在第一组和第二组查找表之间。 多路复用器电路可以与来自第一组查找表的输出信号并行地接收可编程逻辑区域输入信号，并且可以向第二组查找表提供相应的所选择的信号。 可编程逻辑区域输入信号可以由第一组和第二组查找表共享。 逻辑电路可以耦合到第一组和第二组查找表的输出。 逻辑电路可以被配置为逻辑地组合来自第一组和第二组查找表的输出信号。

公开(公告)号：US08427213B2

公开(公告)日：2013-04-23

申请号：US13347626

申请日：2012-01-10

申请人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

发明人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

IPC分类号： H03K3/00

CPC分类号： H03K3/0375

摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器显示出通过条件降低的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。

公开(公告)号：US20110089974A1

公开(公告)日：2011-04-21

申请号：US12976752

申请日：2010-12-22

申请人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

发明人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

IPC分类号： H03K19/00 ,  H03K3/00

CPC分类号： H03K3/0375

摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器具有降低的竞争条件的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。

公开(公告)号：US07868655B2

公开(公告)日：2011-01-11

申请号：US12505451

申请日：2009-07-17

申请人： David Lewis ,  David Cashman

发明人： David Lewis ,  David Cashman

IPC分类号： H03K19/173 ,  H03K19/098 ,  H03L7/00 ,  H03B19/00

CPC分类号： H03K19/1733 ,  G06F17/5054 ,  G06F2217/84

摘要： Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.

摘要翻译： 为诸如可编程逻辑器件的电路提供可配置的时间借用触发器。 触发器可以基于可配置的延迟电路和两个锁存器，或者可以基于可配置的脉冲发生电路和单个锁存器。 在基于两个锁存器的设计中，串联布置第一和第二闩锁。 使用可配置的延迟电路延迟时钟信号。 已经加载了配置数据的可编程存储器元件可以用于调整可配置延迟电路产生多少延迟。 时钟信号的延迟版本被提供给与第一锁存器相关联的时钟输入。 第二个锁存器具有时钟输入端，无延迟地接收时钟信号。 在基于单个锁存器的设计中，可配置脉冲发生电路接收触发器的时钟信号，并为锁存器产生相应的时钟脉冲。

公开(公告)号：US07456653B2

公开(公告)日：2008-11-25

申请号：US11684424

申请日：2007-03-09

申请人： David Lewis ,  David Cashman

发明人： David Lewis ,  David Cashman

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A PLD with LAB interconnect lines that span adjacent LABs in the array and that have the ability to interconnect two logic elements in the different LABs. The PLD includes a plurality of LABs arranged in an array and a plurality of inter-LAB lines interconnecting the LABs of the array. Each of the LABs include a predetermined number of logic elements, one or more control signals distributed among the predetermined number of logic elements in the LAB, and LAB lines spanning between logic elements in different LABs in the array. In various embodiments, the LAB lines are arranged in a staggered pattern with a predetermined pitch between the lines. In other embodiments, the control signals of adjacent LABs can overlap, allowing control signals to be routed to the logic elements of adjacent LABs.

摘要翻译： 具有LAB互连线的PLD，跨越阵列中的相邻LAB并具有互连不同LAB中的两个逻辑元件的能力。 PLD包括布置在阵列中的多个LAB和将阵列的LAB互连的多个LAB线。 每个LAB包括预定数量的逻辑元件，分布在LAB中的预定数量的逻辑元件中的一个或多个控制信号，以及跨越阵列中不同LAB中的逻辑元件之间的LAB线。 在各种实施例中，LAB线以两条线之间的预定间距以交错图案排列。 在其他实施例中，相邻LAB的控制信号可以重叠，允许控制信号被路由到相邻LAB的逻辑元件。

公开(公告)号：US20080238476A1

公开(公告)日：2008-10-02

申请号：US11731125

申请日：2007-03-30

申请人： David Lewis ,  David Cashman

发明人： David Lewis ,  David Cashman

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/1733 ,  G06F17/5054 ,  G06F2217/84

摘要： Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.

摘要翻译： 为诸如可编程逻辑器件的电路提供可配置的时间借用触发器。 触发器可以基于可配置的延迟电路和两个锁存器，或者可以基于可配置的脉冲发生电路和单个锁存器。 在基于两个锁存器的设计中，串联布置第一和第二闩锁。 使用可配置的延迟电路延迟时钟信号。 已经加载了配置数据的可编程存储器元件可以用于调整可配置延迟电路产生多少延迟。 时钟信号的延迟版本被提供给与第一锁存器相关联的时钟输入。 第二个锁存器具有时钟输入端，无延迟地接收时钟信号。 在基于单个锁存器的设计中，可配置脉冲发生电路接收触发器的时钟信号，并为锁存器产生相应的时钟脉冲。