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公开(公告)号：US09940138B2
公开(公告)日：2018-04-10
申请号：US12420762
申请日：2009-04-08
申请人： Pedro Lopez , Carlos Madriles , Alejandro Martinez , Raul Martinez , Josep M. Codina , Enric Gibert Codina , Fernando Latorre , Antonio Gonzalez
发明人： Pedro Lopez , Carlos Madriles , Alejandro Martinez , Raul Martinez , Josep M. Codina , Enric Gibert Codina , Fernando Latorre , Antonio Gonzalez
CPC分类号： G06F9/3863 , G06F9/30043 , G06F9/3842 , G06F9/3851 , G06F11/1402
摘要： Methods and apparatus are disclosed for using a register checkpointing mechanism to resolve multithreading mis-speculations. Valid architectural state is recovered and execution is rolled back. Some embodiments include memory to store checkpoint data. Multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. Threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function. Threads then execute one or more checkpoint read instructions to copy data from a valid checkpoint storage area into the registers necessary to recover a valid architectural state, from which execution may resume.
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12.发明授权Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution 有权将顺序程序分解为多个线程的系统，方法和装置，执行所述线程，并重建顺序执行公开(公告)号：US08909902B2
公开(公告)日：2014-12-09
申请号：US12624804
申请日：2009-11-24
申请人： Fernando Latorre , Josep M. Codina , Enric Gibert Codina , Pedro Lopez , Carlos Madriles , Alejandro Martinez Vincente , Raul Martinez , Antonio Gonzalez
发明人： Fernando Latorre , Josep M. Codina , Enric Gibert Codina , Pedro Lopez , Carlos Madriles , Alejandro Martinez Vincente , Raul Martinez , Antonio Gonzalez
IPC分类号： G06F9/40
CPC分类号： G06F9/3842 , G06F8/433 , G06F8/452 , G06F8/457 , G06F9/3851 , G06F9/3861
摘要： Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.
摘要翻译： 描述用于将顺序程序分解成多个线程，执行这些线程以及重建线程的顺序执行的系统，方法和装置。 多个数据高速缓存单元（DCU）存储推测执行的线程的本地退出指令。 合并级别缓存（MLC）合并来自DCU的行的数据。 核心内存一致性模块（ICMC）全局退出MLC中推测执行线程的指令。
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公开(公告)号：US20100115247A1
公开(公告)日：2010-05-06
申请号：US12263418
申请日：2008-10-31
申请人： Pedro Lopez , F. Jesus Sanchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio Gonzalez
发明人： Pedro Lopez , F. Jesus Sanchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio Gonzalez
CPC分类号： G06F11/3419 , G06F11/3466 , G06F2201/81 , G06F2201/88 , G06F2201/885
摘要： Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.
摘要翻译： 描述与热代码检测的替换策略有关的方法和装置。 在一些实施例中，可以确定存储在存储单元中的多个条目中的哪个条目将被替换。 这些条目可以对应于热代码，并且可以存储对应于热代码的年龄和执行频率信息。 还描述和要求保护其他实施例。
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公开(公告)号：US08612698B2
公开(公告)日：2013-12-17
申请号：US12263418
申请日：2008-10-31
申请人： Pedro Lopez , F. Jesús Sánchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio González
发明人： Pedro Lopez , F. Jesús Sánchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio González
CPC分类号： G06F11/3419 , G06F11/3466 , G06F2201/81 , G06F2201/88 , G06F2201/885
摘要： Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.
摘要翻译： 描述与热代码检测的替换策略有关的方法和装置。 在一些实施例中，可以确定存储在存储单元中的多个条目中的哪个条目将被替换。 这些条目可以对应于热代码，并且可以存储对应于热代码的年龄和执行频率信息。 还描述和要求保护其他实施例。
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15.发明授权Method and apparatus for flexible, accurate, and/or efficient code profiling 有权用于灵活，准确和/或有效的代码分析的方法和装置公开(公告)号：US08898646B2
公开(公告)日：2014-11-25
申请号：US12976799
申请日：2010-12-22
CPC分类号： G06F11/348 , G06F11/3409 , G06F11/3466 , G06F2201/86 , G06F2201/865
摘要： An apparatus and method for profiling program code. In particular, an apparatus according to one embodiment comprises a filtering component identifying a first set of instructions for which profiling is desired wherein, in response to detecting that an instruction has been retired, the filtering component determines whether the instruction is within the first set of instructions for which profiling is desired; an event selection component detecting an event in response to the instruction retiring, the event selection component generating event signals in response to a designated event; and a profiling component recording the occurrence or not occurrence of the event within a first storage device responsive to signals from the filtering component and/or the event selection component.
摘要翻译： 用于分析程序代码的设备和方法。 具体地，根据一个实施例的装置包括识别期望进行分析的第一组指令的过滤部件，其中响应于检测到指令已经停止，滤波部件确定该指令是否在第一组中 需要进行分析的说明; 事件选择部件响应于所述指令重新检测事件，所述事件选择部件响应于指定的事件产生事件信号; 以及响应于来自过滤组件和/或事件选择组件的信号，在第一存储设备内记录事件的发生或不发生的分析组件。
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16.发明申请METHOD AND APPARATUS FOR FLEXIBLE, ACCURATE, AND/OR EFFICIENT CODE PROFILING 有权灵活，精确和/或有效的代码分析的方法和装置公开(公告)号：US20120167058A1
公开(公告)日：2012-06-28
申请号：US12976799
申请日：2010-12-22
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , G06F11/3409 , G06F11/3466 , G06F2201/86 , G06F2201/865
摘要： An apparatus and method for profiling program code. In particular, an apparatus according to one embodiment comprises a filtering component identifying a first set of instructions for which profiling is desired wherein, in response to detecting that an instruction has been retired, the filtering component determines whether the instruction is within the first set of instructions for which profiling is desired; an event selection component detecting an event in response to the instruction retiring, the event selection component generating event signals in response to a designated event; and a profiling component recording the occurrence or not occurrence of the event within a first storage device responsive to signals from the filtering component and/or the event selection component.
摘要翻译： 用于分析程序代码的设备和方法。 具体地，根据一个实施例的装置包括识别期望进行分析的第一组指令的过滤部件，其中响应于检测到指令已经停止，滤波部件确定该指令是否在第一组中 需要进行分析的说明; 事件选择部件响应于所述指令重新检测事件，所述事件选择部件响应于指定的事件产生事件信号; 以及响应于来自过滤组件和/或事件选择组件的信号，在第一存储设备内记录事件的发生或不发生的分析组件。
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17.发明申请公开(公告)号：US20090150335A1
公开(公告)日：2009-06-11
申请号：US11951614
申请日：2007-12-06
CPC分类号： G06F12/1027 , G06F12/0875
摘要： An apparatus comprising a first search logic to search for a first entry for a first page containing a first code region in a first data structure to determine whether a first indicator in the first entry is set to a first value; an adder logic to add the first entry to the first data structure, in response to failing to find the first entry in the first data structure; a second search logic to search for a second entry for the first code region in a second data structure, in response to determining that the first indicator is set to the first value, wherein one or more optimized code regions corresponding to the first page from a code cache are to be removed in response to determining that the first page may have been modified, and wherein the first indicator is to be set to a second value.
摘要翻译： 一种装置，包括：第一搜索逻辑，用于搜索包含第一数据结构中的第一代码区域的第一页面的第一条目，以确定第一条目中的第一指示符是否被设置为第一值; 响应于未能找到第一数据结构中的第一条目而将第一条目添加到第一数据结构的加法器逻辑; 响应于确定所述第一指示符被设置为所述第一值，搜索第二数据结构中的所述第一代码区域的第二条目的第二搜索逻辑，其中对应于来自第一值的第一页的一个或多个优化代码区域 响应于确定第一页面可能被修改而要删除代码高速缓存，并且其中第一指示符将被设置为第二值。
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公开(公告)号：US07895415B2
公开(公告)日：2011-02-22
申请号：US11705987
申请日：2007-02-14
申请人： Antonio Gonzalez , Josep M. Codina , Pedro Lopez , Fernando Latorre , Jose-Alejandro Pineiro , Enric Gibert , Jaume Abella , Jaideep Moses , Donald Newell , Ravishankar Iyer , Ramesh G. Illikkal , Srihari Makineni
发明人： Antonio Gonzalez , Josep M. Codina , Pedro Lopez , Fernando Latorre , Jose-Alejandro Pineiro , Enric Gibert , Jaume Abella , Jaideep Moses , Donald Newell , Ravishankar Iyer , Ramesh G. Illikkal , Srihari Makineni
CPC分类号： G06F9/3851 , G06F9/3009 , G06F12/0842
摘要： Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.
摘要翻译： 描述与基于缓存共享的线程控制相关联的装置和计算系统。 一个实施例包括存储线程控制指令的存储器和执行线程控制指令的处理器。 处理器耦合到存储器。 处理器包括第一单元，用于动态地确定多线程计算系统中的线程之间的高速缓存共享行为，以及第二单元，以动态地控制多线程计算系统中的一组线程的组合。 该组线程的组合至少部分地基于缓存共享行为所表现的线程亲和性。 线程控制指令控制第一单元和第二单元的操作。
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公开(公告)号：US20080195849A1
公开(公告)日：2008-08-14
申请号：US11705987
申请日：2007-02-14
申请人： Antonio Gonzalez , Josep M. Codina , Pedro Lopez , Fernando Latorre , Jose-Alejandro Pineiro , Enric Gibert , Jaume Abella , Jaideep Moses , Donald Newell , Ravishankar Iyer , Ramesh G. Illikkal , Srihari Makineni
发明人： Antonio Gonzalez , Josep M. Codina , Pedro Lopez , Fernando Latorre , Jose-Alejandro Pineiro , Enric Gibert , Jaume Abella , Jaideep Moses , Donald Newell , Ravishankar Iyer , Ramesh G. Illikkal , Srihari Makineni
CPC分类号： G06F9/3851 , G06F9/3009 , G06F12/0842
摘要： Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.
摘要翻译： 描述与基于缓存共享的线程控制相关联的装置和计算系统。 一个实施例包括存储线程控制指令的存储器和执行线程控制指令的处理器。 处理器耦合到存储器。 处理器包括第一单元，用于动态地确定多线程计算系统中的线程之间的高速缓存共享行为，以及第二单元，以动态地控制多线程计算系统中的一组线程的组合。 该组线程的组合至少部分地基于缓存共享行为所表现的线程亲和性。 线程控制指令控制第一单元和第二单元的操作。
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公开(公告)号：US20140281434A1
公开(公告)日：2014-09-18
申请号：US13994193
申请日：2013-03-15
IPC分类号： G06F9/30
CPC分类号： G06F9/30076 , G06F8/443
摘要： A mechanism for generating a path profile is disclosed. A profiling module may insert profiling instructions into instruction blocks. The profiling instructions may generate a path identifier as a processor executes an execution path executes a sequence or path of instruction blocks). A path identifier module may add path identifiers to path identifier data, such as a table, and may track the number of times an execution path associated with the path identifier is executed. The profiling module may periodically copy and/or modify the path identifier data and may generate a path profile based on the path identifier data
摘要翻译： 公开了一种用于产生路径轮廓的机构。 分析模块可以将分析指令插入到指令块中。 当处理器执行执行路径执行指令块的序列或路径时，分析指令可以生成路径标识符）。 路径标识符模块可以将诸如表的路径标识符数据的路径标识符添加，并且可以跟踪执行与路径标识符相关联的执行路径的次数。 分析模块可以周期性地复制和/或修改路径标识符数据，并且可以基于路径标识符数据生成路径简档
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