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公开(公告)号：US09811341B2
公开(公告)日：2017-11-07
申请号：US13995649
申请日：2011-12-29
Applicant: Kyriakos A. Stavrou , Enric Gibert Codina , Josep M. Codina , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos E. Kotselidis , Fernando Latorre , Pedro Lopez , Marc Lupon , Carlos Madriles Gimeno , Grigorios Magklis , Pedro Marcuello , Alejandro Martinez Vicente , Raul Martinez , Daniel Ortega , Demos Pavlou , Georgios Tournavitis , Polychronis Xekalakis
Inventor： Kyriakos A. Stavrou , Enric Gibert Codina , Josep M. Codina , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos E. Kotselidis , Fernando Latorre , Pedro Lopez , Marc Lupon , Carlos Madriles Gimeno , Grigorios Magklis , Pedro Marcuello , Alejandro Martinez Vicente , Raul Martinez , Daniel Ortega , Demos Pavlou , Georgios Tournavitis , Polychronis Xekalakis
IPC: G06F9/38 , G06F9/30 , G06F12/0862
CPC classification number: G06F9/3804 , G06F9/30047 , G06F9/3017 , G06F9/3802 , G06F9/3806 , G06F9/3848 , G06F12/0862 , G06F2212/452
Abstract: Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
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公开(公告)号：US20140019721A1
公开(公告)日：2014-01-16
申请号：US13995649
申请日：2011-12-29
Applicant: Kyriakos A. Stavrou , Enric Gibert Codina , Josep M. Codina , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos E. Kotselidis , Fernando Latorre , Pedro Lopez , Marc Lupon , Carlos Madriles gimeno , Grigorios Magklis , Pedro Marcuello , Alejandro Martinez Vicente , Raul Martinez , Daniel Ortega , Demos Pavlou , Georgios Tournavitis , Polychronis Xekalakis
Inventor： Kyriakos A. Stavrou , Enric Gibert Codina , Josep M. Codina , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos E. Kotselidis , Fernando Latorre , Pedro Lopez , Marc Lupon , Carlos Madriles gimeno , Grigorios Magklis , Pedro Marcuello , Alejandro Martinez Vicente , Raul Martinez , Daniel Ortega , Demos Pavlou , Georgios Tournavitis , Polychronis Xekalakis
IPC: G06F9/38
CPC classification number: G06F9/3804 , G06F9/30047 , G06F9/3017 , G06F9/3802 , G06F9/3806 , G06F9/3848 , G06F12/0862 , G06F2212/452
Abstract: Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: indentifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
Abstract translation: 公开了一种用于从指令高速缓存管理指令高速缓存预取的装置和方法。 处理器可以包括：预取引擎; 预测分支结果的分支预测引擎; 和动态优化器。 动态优化器可用于控制：识别公共指令高速缓存未命中并将预取引擎的预取指令插入指令高速缓存。
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公开(公告)号：US08612698B2
公开(公告)日：2013-12-17
申请号：US12263418
申请日：2008-10-31
Applicant: Pedro Lopez , F. Jesús Sánchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio González
Inventor： Pedro Lopez , F. Jesús Sánchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio González
CPC classification number: G06F11/3419 , G06F11/3466 , G06F2201/81 , G06F2201/88 , G06F2201/885
Abstract: Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.
Abstract translation: 描述与热代码检测的替换策略有关的方法和装置。 在一些实施例中，可以确定存储在存储单元中的多个条目中的哪个条目将被替换。 这些条目可以对应于热代码，并且可以存储对应于热代码的年龄和执行频率信息。 还描述和要求保护其他实施例。
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公开(公告)号：US07895415B2
公开(公告)日：2011-02-22
申请号：US11705987
申请日：2007-02-14
Applicant: Antonio Gonzalez , Josep M. Codina , Pedro Lopez , Fernando Latorre , Jose-Alejandro Pineiro , Enric Gibert , Jaume Abella , Jaideep Moses , Donald Newell , Ravishankar Iyer , Ramesh G. Illikkal , Srihari Makineni
Inventor： Antonio Gonzalez , Josep M. Codina , Pedro Lopez , Fernando Latorre , Jose-Alejandro Pineiro , Enric Gibert , Jaume Abella , Jaideep Moses , Donald Newell , Ravishankar Iyer , Ramesh G. Illikkal , Srihari Makineni
CPC classification number: G06F9/3851 , G06F9/3009 , G06F12/0842
Abstract: Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.
Abstract translation: 描述与基于缓存共享的线程控制相关联的装置和计算系统。 一个实施例包括存储线程控制指令的存储器和执行线程控制指令的处理器。 处理器耦合到存储器。 处理器包括第一单元，用于动态地确定多线程计算系统中的线程之间的高速缓存共享行为，以及第二单元，以动态地控制多线程计算系统中的一组线程的组合。 该组线程的组合至少部分地基于缓存共享行为所表现的线程亲和性。 线程控制指令控制第一单元和第二单元的操作。
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公开(公告)号：US20100005277A1
公开(公告)日：2010-01-07
申请号：US12446930
申请日：2006-10-27
Applicant: Enric Gibert , Josep M. Codina , Fernando Latorre , José Alejandro Pineiro , Pedro López , Antonio González
Inventor： Enric Gibert , Josep M. Codina , Fernando Latorre , José Alejandro Pineiro , Pedro López , Antonio González
CPC classification number: G06F9/3851 , G06F9/3838 , G06F9/526
Abstract: In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括在执行第二线程时访问与第一线程相关联的寄存器的方法。 在一个这样的实施例中，一种方法可以包括：如果与源操作数相关联的同步指示符表示第二线程的生成器操作的不完备，则可以防止第一线程的指令从第二线程的寄存器文件访问源操作数执行 线程，并且如果同步指示符指示第二线程的生成器操作的完成，则执行指令。 描述和要求保护其他实施例。
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Patent Agency Ranking
6.发明授权Method and apparatus for flexible, accurate, and/or efficient code profiling 有权用于灵活，准确和/或有效的代码分析的方法和装置公开(公告)号：US08898646B2
公开(公告)日：2014-11-25
申请号：US12976799
申请日：2010-12-22
Applicant: Enric Gibert Codina , Josep M. Codina , Carlos Madriles , Raul Martinez
Inventor： Enric Gibert Codina , Josep M. Codina , Carlos Madriles , Raul Martinez
CPC classification number: G06F11/348 , G06F11/3409 , G06F11/3466 , G06F2201/86 , G06F2201/865
Abstract: An apparatus and method for profiling program code. In particular, an apparatus according to one embodiment comprises a filtering component identifying a first set of instructions for which profiling is desired wherein, in response to detecting that an instruction has been retired, the filtering component determines whether the instruction is within the first set of instructions for which profiling is desired; an event selection component detecting an event in response to the instruction retiring, the event selection component generating event signals in response to a designated event; and a profiling component recording the occurrence or not occurrence of the event within a first storage device responsive to signals from the filtering component and/or the event selection component.
Abstract translation: 用于分析程序代码的设备和方法。 具体地，根据一个实施例的装置包括识别期望进行分析的第一组指令的过滤部件，其中响应于检测到指令已经停止，滤波部件确定该指令是否在第一组中 需要进行分析的说明; 事件选择部件响应于所述指令重新检测事件，所述事件选择部件响应于指定的事件产生事件信号; 以及响应于来自过滤组件和/或事件选择组件的信号，在第一存储设备内记录事件的发生或不发生的分析组件。
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7.发明申请METHOD, APPARATUS AND SYSTEM FOR SELECTIVE EXECUTION OF A COMMIT INSTRUCTION 审中-公开方法，选择性执行委托指令的方法和系统公开(公告)号：US20140156976A1
公开(公告)日：2014-06-05
申请号：US13995441
申请日：2011-12-22
Applicant: Enric Gibert Codina , Josep M. Codina , Fernando Latorre , Pedro Marcuello , Pedro Lopez , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos E. Kotselidis , Marc Lupon , Carlos Madriles Gimeno , Grigorios Magklis , Alejandro Martinez Vicente , Raul Martinez , Daniel Ortega , Demos Pavlou , Kyriakos A. Stavrou , Georgios Tournavitis , Polychronis Xekalakis
Inventor： Enric Gibert Codina , Josep M. Codina , Fernando Latorre , Pedro Marcuello , Pedro Lopez , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos E. Kotselidis , Marc Lupon , Carlos Madriles Gimeno , Grigorios Magklis , Alejandro Martinez Vicente , Raul Martinez , Daniel Ortega , Demos Pavlou , Kyriakos A. Stavrou , Georgios Tournavitis , Polychronis Xekalakis
IPC: G06F9/30
CPC classification number: G06F9/30145 , G06F9/30087 , G06F9/30185 , G06F9/3842 , G06F9/3857 , G06F9/3863
Abstract: Techniques and mechanisms for a processor to determine whether a commit action is to be performed. In an embodiment, a processor performs operations to determine whether a commit instruction is for contingent performance of a commit action. In another embodiment, one or more conditions of processor state are evaluated in response to determining that the commit instruction is for contingent performance of the commit action, where the evaluation is performed to determine whether the commit action indicated by the commit instruction is to be performed.
Abstract translation: 处理器确定是否执行提交动作的技术和机制。 在一个实施例中，处理器执行操作以确定提交指令是否用于或然执行提交动作。 在另一个实施例中，响应于确定提交指令用于提交动作的或然执行来评估处理器状态的一个或多个条件，其中执行评估以确定是否要执行由提交指令指示的提交动作 。
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8.发明申请METHOD AND APPARATUS FOR FLEXIBLE, ACCURATE, AND/OR EFFICIENT CODE PROFILING 有权灵活，精确和/或有效的代码分析的方法和装置公开(公告)号：US20120167058A1
公开(公告)日：2012-06-28
申请号：US12976799
申请日：2010-12-22
Applicant: Enric Gibert Codina , Josep M. Codina , Carlos Madriles , Raul Martinez
Inventor： Enric Gibert Codina , Josep M. Codina , Carlos Madriles , Raul Martinez
IPC: G06F9/44
CPC classification number: G06F11/348 , G06F11/3409 , G06F11/3466 , G06F2201/86 , G06F2201/865
Abstract: An apparatus and method for profiling program code. In particular, an apparatus according to one embodiment comprises a filtering component identifying a first set of instructions for which profiling is desired wherein, in response to detecting that an instruction has been retired, the filtering component determines whether the instruction is within the first set of instructions for which profiling is desired; an event selection component detecting an event in response to the instruction retiring, the event selection component generating event signals in response to a designated event; and a profiling component recording the occurrence or not occurrence of the event within a first storage device responsive to signals from the filtering component and/or the event selection component.
Abstract translation: 用于分析程序代码的设备和方法。 具体地，根据一个实施例的装置包括识别期望进行分析的第一组指令的过滤部件，其中响应于检测到指令已经停止，滤波部件确定该指令是否在第一组中 需要进行分析的说明; 事件选择部件响应于所述指令重新检测事件，所述事件选择部件响应于指定的事件产生事件信号; 以及响应于来自过滤组件和/或事件选择组件的信号，在第一存储设备内记录事件的发生或不发生的分析组件。
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公开(公告)号：US20100115247A1
公开(公告)日：2010-05-06
申请号：US12263418
申请日：2008-10-31
Applicant: Pedro Lopez , F. Jesus Sanchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio Gonzalez
Inventor： Pedro Lopez , F. Jesus Sanchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio Gonzalez
CPC classification number: G06F11/3419 , G06F11/3466 , G06F2201/81 , G06F2201/88 , G06F2201/885
Abstract: Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.
Abstract translation: 描述与热代码检测的替换策略有关的方法和装置。 在一些实施例中，可以确定存储在存储单元中的多个条目中的哪个条目将被替换。 这些条目可以对应于热代码，并且可以存储对应于热代码的年龄和执行频率信息。 还描述和要求保护其他实施例。
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公开(公告)号：US20140281434A1
公开(公告)日：2014-09-18
申请号：US13994193
申请日：2013-03-15
Applicant: Carlos Madriles , Josep M. Codina , Christos E Kotselidis , Alejandro Martinez Vicente
IPC: G06F9/30
CPC classification number: G06F9/30076 , G06F8/443
Abstract: A mechanism for generating a path profile is disclosed. A profiling module may insert profiling instructions into instruction blocks. The profiling instructions may generate a path identifier as a processor executes an execution path executes a sequence or path of instruction blocks). A path identifier module may add path identifiers to path identifier data, such as a table, and may track the number of times an execution path associated with the path identifier is executed. The profiling module may periodically copy and/or modify the path identifier data and may generate a path profile based on the path identifier data
Abstract translation: 公开了一种用于产生路径轮廓的机构。 分析模块可以将分析指令插入到指令块中。 当处理器执行执行路径执行指令块的序列或路径时，分析指令可以生成路径标识符）。 路径标识符模块可以将诸如表的路径标识符数据的路径标识符添加，并且可以跟踪执行与路径标识符相关联的执行路径的次数。 分析模块可以周期性地复制和/或修改路径标识符数据，并且可以基于路径标识符数据生成路径简档
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