公开(公告)号：US06982193B2

公开(公告)日：2006-01-03

申请号：US10841670

申请日：2004-05-10

申请人： Zia Hossain ,  Prasad Venkatraman

发明人： Zia Hossain ,  Prasad Venkatraman

IPC分类号： H01L21/332 ,  H01L21/76 ,  H01L21/22

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66712 ,  H01L29/7802

摘要： In one embodiment, a transistor is formed to have alternating depletion and conduction regions that are formed by doping the depletion and conduction regions through an opening in a substrate of the transistor.

摘要翻译： 在一个实施例中，晶体管被形成为具有通过将晶体管的衬底中的开口掺杂到耗尽和导电区域而形成的交替的耗尽和导电区域。

公开(公告)号：US09029215B2

公开(公告)日：2015-05-12

申请号：US13471105

申请日：2012-05-14

申请人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

发明人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

摘要翻译： 在一个实施例中，形成半导体器件的方法包括沿着沟槽的表面形成沟槽和电介质层。 屏蔽电极形成在沟槽的下部，电介质层从沟槽的上侧壁表面去除。 栅极电介质层沿沟槽的上表面形成。 沿着栅极电介质层形成耐氧化间隔物。 此后，使用局部氧化在屏蔽电极上方形成间隔电介质层。 氧化步骤增加了栅极电介质层的下部的厚度。 在形成邻近栅极电介质层的栅电极之前去除抗氧化间隔物。

公开(公告)号：US07714381B2

公开(公告)日：2010-05-11

申请号：US11095135

申请日：2005-04-01

申请人： Francine Y. Robb ,  Stephen P. Robb ,  Prasad Venkatraman ,  Zia Hossain

发明人： Francine Y. Robb ,  Stephen P. Robb ,  Prasad Venkatraman ,  Zia Hossain

IPC分类号： H01L27/105

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0878 ,  H01L29/66734

摘要： In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

摘要翻译： 在一个实施例中，在具有其它晶体管的半导体衬底上形成垂直功率晶体管。 垂直功率晶体管下面的半导体层的一部分被掺杂以为垂直功率晶体管提供低导通电阻。

公开(公告)号：US20080277694A1

公开(公告)日：2008-11-13

申请号：US11746437

申请日：2007-05-09

申请人： Zia Hossain ,  Francine Y. Robb ,  Prasad Venkatraman

发明人： Zia Hossain ,  Francine Y. Robb ,  Prasad Venkatraman

IPC分类号： H01L27/095 ,  H01L21/44 ,  H01L29/76

CPC分类号： H01L27/0629 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/8249

摘要： A semiconductor component that includes a Schottky device, an edge termination structure, a non-Schottky semiconductor device, combinations thereof and a method of manufacturing the semiconductor component. A semiconductor material includes a first epitaxial layer disposed on a semiconductor substrate and a second epitaxial layer disposed on the first epitaxial layer. The second epitaxial layer has a higher resistivity than the semiconductor substrate. A Schottky device and a non-Schottky semiconductor device are manufactured from the second epitaxial layer. In accordance with another embodiment, a semiconductor material includes an epitaxial layer disposed over a semiconductor substrate. The epitaxial layer has a higher resistivity than the semiconductor substrate. A doped region is formed in the epitaxial layer. A Schottky device and a non-Schottky semiconductor device are manufactured from the epitaxial layer.

摘要翻译： 一种包括肖特基器件，边缘端接结构，非肖特基半导体器件及其组合的半导体部件和制造半导体部件的方法。 半导体材料包括设置在半导体衬底上的第一外延层和设置在第一外延层上的第二外延层。 第二外延层具有比半导体衬底更高的电阻率。 由第二外延层制造肖特基器件和非肖特基半导体器件。 根据另一实施例，半导体材料包括设置在半导体衬底上的外延层。 外延层具有比半导体衬底更高的电阻率。 在外延层中形成掺杂区域。 由外延层制造肖特基器件和非肖特基半导体器件。

公开(公告)号：US20100133610A1

公开(公告)日：2010-06-03

申请号：US12696816

申请日：2010-01-29

申请人： Francine Y. Robb ,  Stephen P. Robb ,  Prasad Venkatraman ,  Zia Hossain

发明人： Francine Y. Robb ,  Stephen P. Robb ,  Prasad Venkatraman ,  Zia Hossain

IPC分类号： H01L27/088 ,  H01L21/77 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0878 ,  H01L29/66734

摘要： In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

摘要翻译： 在一个实施例中，在具有其它晶体管的半导体衬底上形成垂直功率晶体管。 垂直功率晶体管下面的半导体层的一部分被掺杂以为垂直功率晶体管提供低导通电阻。

公开(公告)号：US20060220140A1

公开(公告)日：2006-10-05

申请号：US11095135

申请日：2005-04-01

申请人： Francine Robb ,  Stephan Robb ,  Prasad Venkatraman ,  Zia Hossain

发明人： Francine Robb ,  Stephan Robb ,  Prasad Venkatraman ,  Zia Hossain

IPC分类号： H01L29/423

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0878 ,  H01L29/66734

摘要： In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

摘要翻译： 在一个实施例中，在具有其它晶体管的半导体衬底上形成垂直功率晶体管。 垂直功率晶体管下面的半导体层的一部分被掺杂以为垂直功率晶体管提供低导通电阻。

公开(公告)号：US08928050B2

公开(公告)日：2015-01-06

申请号：US13794103

申请日：2013-03-11

申请人： Gary H. Loechelt ,  Prasad Venkatraman ,  Zia Hossain ,  Gordon M. Grivna

发明人： Gary H. Loechelt ,  Prasad Venkatraman ,  Zia Hossain ,  Gordon M. Grivna

IPC分类号： H01L29/76 ,  H01L27/02

CPC分类号： H01L27/0255 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/872

摘要： An electronic device can include a semiconductor layer having a primary surface, and a Schottky contact comprising a metal-containing member in contact with a horizontally-oriented lightly doped region within the semiconductor layer and lying adjacent to the primary surface. In an embodiment, the metal-containing member lies within a recess in the semiconductor layer and contacts the horizontally-oriented lightly doped region along a sidewall of the recess. In other embodiment, the Schottky contact may not be formed within a recess, and a doped region may be formed within the semiconductor layer under the horizontally-oriented lightly doped region and have a conductivity type opposite the horizontally-oriented lightly doped region. The Schottky contacts can be used in conjunction with power transistors in a switching circuit, such as a high-frequency voltage regulator.

摘要翻译： 电子器件可以包括具有主表面的半导体层和包含与半导体层内的水平取向的轻掺杂区域接触并且位于主表面附近的含金属元件的肖特基接触。 在一个实施例中，含金属的构件位于半导体层中的凹部内，并沿凹槽的侧壁接触水平取向的轻掺杂区域。 在另一实施例中，肖特基接触可以不形成在凹槽内，并且可以在水平取向的轻掺杂区域之下的半导体层内形成掺杂区域，并且具有与水平取向的轻掺杂区域相反的导电类型。 肖特基触点可以与开关电路中的功率晶体管一起使用，例如高频电压调节器。

公开(公告)号：US20140252484A1

公开(公告)日：2014-09-11

申请号：US13794103

申请日：2013-03-11

申请人： Gary H. Loechelt ,  Prasad Venkatraman ,  Zia Hossain ,  Gordon M. Grivna

发明人： Gary H. Loechelt ,  Prasad Venkatraman ,  Zia Hossain ,  Gordon M. Grivna

IPC分类号： H01L27/02

CPC分类号： H01L27/0255 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/872

摘要： An electronic device can include a semiconductor layer having a primary surface, and a Schottky contact comprising a metal-containing member in contact with a horizontally-oriented lightly doped region within the semiconductor layer and lying adjacent to the primary surface. In an embodiment, the metal-containing member lies within a recess in the semiconductor layer and contacts the horizontally-oriented lightly doped region along a sidewall of the recess. In other embodiment, the Schottky contact may not be formed within a recess, and a doped region may be formed within the semiconductor layer under the horizontally-oriented lightly doped region and have a conductivity type opposite the horizontally-oriented lightly doped region. The Schottky contacts can be used in conjunction with power transistors in a switching circuit, such as a high-frequency voltage regulator.

摘要翻译： 电子器件可以包括具有主表面的半导体层和包含与半导体层内的水平取向的轻掺杂区域接触并且位于主表面附近的含金属元件的肖特基接触。 在一个实施例中，含金属的构件位于半导体层中的凹部内，并沿凹槽的侧壁接触水平取向的轻掺杂区域。 在另一实施例中，肖特基接触可以不形成在凹槽内，并且可以在水平取向的轻掺杂区域之下的半导体层内形成掺杂区域，并且具有与水平取向的轻掺杂区域相反的导电类型。 肖特基触点可以与开关电路中的功率晶体管一起使用，例如高频电压调节器。

公开(公告)号：US20130302958A1

公开(公告)日：2013-11-14

申请号：US13471105

申请日：2012-05-14

申请人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

发明人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

IPC分类号： H01L21/336 ,  H01L21/283

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

摘要翻译： 在一个实施例中，形成半导体器件的方法包括沿着沟槽的表面形成沟槽和电介质层。 屏蔽电极形成在沟槽的下部，电介质层从沟槽的上侧壁表面去除。 栅极电介质层沿沟槽的上表面形成。 沿着栅极电介质层形成耐氧化间隔物。 此后，使用局部氧化在屏蔽电极上方形成间隔电介质层。 氧化步骤增加了栅极电介质层的下部的厚度。 在形成邻近栅极电介质层的栅电极之前去除抗氧化间隔物。

公开(公告)号：US08138033B2

公开(公告)日：2012-03-20

申请号：US11746437

申请日：2007-05-09

申请人： Zia Hossain ,  Francine Y. Robb ,  Prasad Venkatraman

发明人： Zia Hossain ,  Francine Y. Robb ,  Prasad Venkatraman

IPC分类号： H01L21/44 ,  H01L29/76 ,  H01L27/095

CPC分类号： H01L27/0629 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/8249

摘要： A semiconductor component that includes a Schottky device, an edge termination structure, a non-Schottky semiconductor device, combinations thereof and a method of manufacturing the semiconductor component. A semiconductor material includes a first epitaxial layer disposed on a semiconductor substrate and a second epitaxial layer disposed on the first epitaxial layer. The second epitaxial layer has a higher resistivity than the semiconductor substrate. A Schottky device and a non-Schottky semiconductor device are manufactured from the second epitaxial layer. In accordance with another embodiment, a semiconductor material includes an epitaxial layer disposed over a semiconductor substrate. The epitaxial layer has a higher resistivity than the semiconductor substrate. A doped region is formed in the epitaxial layer. A Schottky device and a non-Schottky semiconductor device are manufactured from the epitaxial layer.

摘要翻译： 一种包括肖特基器件，边缘端接结构，非肖特基半导体器件及其组合的半导体部件和制造半导体部件的方法。 半导体材料包括设置在半导体衬底上的第一外延层和设置在第一外延层上的第二外延层。 第二外延层具有比半导体衬底更高的电阻率。 由第二外延层制造肖特基器件和非肖特基半导体器件。 根据另一实施例，半导体材料包括设置在半导体衬底上的外延层。 外延层具有比半导体衬底更高的电阻率。 在外延层中形成掺杂区域。 由外延层制造肖特基器件和非肖特基半导体器件。