公开(公告)号：US09029215B2

公开(公告)日：2015-05-12

申请号：US13471105

申请日：2012-05-14

申请人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

发明人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

摘要翻译： 在一个实施例中，形成半导体器件的方法包括沿着沟槽的表面形成沟槽和电介质层。 屏蔽电极形成在沟槽的下部，电介质层从沟槽的上侧壁表面去除。 栅极电介质层沿沟槽的上表面形成。 沿着栅极电介质层形成耐氧化间隔物。 此后，使用局部氧化在屏蔽电极上方形成间隔电介质层。 氧化步骤增加了栅极电介质层的下部的厚度。 在形成邻近栅极电介质层的栅电极之前去除抗氧化间隔物。

公开(公告)号：US20130302958A1

公开(公告)日：2013-11-14

申请号：US13471105

申请日：2012-05-14

申请人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

发明人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

IPC分类号： H01L21/336 ,  H01L21/283

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

摘要翻译： 在一个实施例中，形成半导体器件的方法包括沿着沟槽的表面形成沟槽和电介质层。 屏蔽电极形成在沟槽的下部，电介质层从沟槽的上侧壁表面去除。 栅极电介质层沿沟槽的上表面形成。 沿着栅极电介质层形成耐氧化间隔物。 此后，使用局部氧化在屏蔽电极上方形成间隔电介质层。 氧化步骤增加了栅极电介质层的下部的厚度。 在形成邻近栅极电介质层的栅电极之前去除抗氧化间隔物。

公开(公告)号：US20110127603A1

公开(公告)日：2011-06-02

申请号：US13022628

申请日：2011-02-07

申请人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

发明人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66727 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

摘要翻译： 包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。 半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。 在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。 屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。 在器件区域中的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。 器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。 器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

公开(公告)号：US20080274417A1

公开(公告)日：2008-11-06

申请号：US12167381

申请日：2008-07-03

申请人： David J. Sturtevant ,  Duane B. Barber ,  Ann I. Kang

发明人： David J. Sturtevant ,  Duane B. Barber ,  Ann I. Kang

IPC分类号： G03F1/00

CPC分类号： G03F7/70433 ,  G03F1/00 ,  G03F1/50 ,  G03F7/70466

摘要： A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third layer pattern is formed on the second mask.

摘要翻译： 根据第一设计制造集成电路的方法。 第一种设计是第一种模式，第一种模式是第一种设计所独有的。 使用在其上的块中形成有第一图案的第一掩模对第一图案成像。 在第一掩模上不形成第一和第二设计的其它图案。 使用在其上的块中形成有第二图案的第二掩模将第二图案成像在基板上。 在第二掩模上形成至少一个第三层图案。

公开(公告)号：US07016054B2

公开(公告)日：2006-03-21

申请号：US10403611

申请日：2003-03-31

申请人： Duane B. Barber ,  Robert C. Muller ,  Mark C. Simmons

发明人： Duane B. Barber ,  Robert C. Muller ,  Mark C. Simmons

IPC分类号： G01B11/02

CPC分类号： G03F7/70625 ,  G01B11/14

摘要： The invention provides a method of measuring a standard critical dimension feature and insuring that this feature is representative of cross-chip average critical dimension size in accordance with an embodiment of the invention. The method includes the steps of incorporating a cluster of CD features, determining a cross-chip average feature size, selecting the CD feature which is closest in size to the cross-chip average CD feature size as the standard feature for in-line measurement, and implementing the CD measurement of the appropriate feature on production wafers.

摘要翻译： 本发明提供了一种测量标准临界尺寸特征并确保该特征代表根据本发明的实施例的跨芯片平均临界尺寸尺寸的方法。 该方法包括以下步骤：结合一组CD特征，确定跨芯片平均特征尺寸，选择与跨平均CD特征尺寸最大的CD特征作为用于在线测量的标准特征， 并在生产晶圆上实施适当特征的CD测量。

公开(公告)号：US07638245B2

公开(公告)日：2009-12-29

申请号：US12167381

申请日：2008-07-03

申请人： David J. Sturtevant ,  Duane B. Barber ,  Ann I. Kang

发明人： David J. Sturtevant ,  Duane B. Barber ,  Ann I. Kang

IPC分类号： G03F1/00 ,  G03F1/14

CPC分类号： G03F7/70433 ,  G03F1/00 ,  G03F1/50 ,  G03F7/70466

摘要： A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third layer pattern is formed on the second mask.

摘要翻译： 根据第一设计制造集成电路的方法。 第一种设计是第一种模式，第一种模式是第一种设计所独有的。 使用在其上的块中形成有第一图案的第一掩模对第一图案成像。 在第一掩模上不形成第一和第二设计的其它图案。 使用在其上的块中形成有第二图案的第二掩模将第二图案成像在基板上。 在第二掩模上形成至少一个第三层图案。

公开(公告)号：US07550236B2

公开(公告)日：2009-06-23

申请号：US10953322

申请日：2004-09-29

申请人： Duane B. Barber ,  Phong T Do ,  Douglas M. Horn

发明人： Duane B. Barber ,  Phong T Do ,  Douglas M. Horn

IPC分类号： G03F1/00 ,  G03F1/14

CPC分类号： G03F1/50

摘要： A mask for exposing a first layer and a second layer on a process substrate, where the first and second layers are two separate layers of an integrated circuit. The mask includes a mask substrate that is substantially completely transmissive to a first wavelength of light and a second wavelength of light. A layer of a first material is disposed on the mask substrate, where the first material is substantially opaque to the first wavelength of light. The layer of the first material is patterned for the first layer. A layer of a second material is disposed on the mask substrate, where the second material is substantially opaque to the second wavelength of light. The layer of the second material is patterned for the second layer, where the layer of the first material and the layer of the second material are aligned on the mask substrate for proper alignment of the first and second layers on the process substrate.

摘要翻译： 用于在处理衬底上暴露第一层和第二层的掩模，其中第一层和第二层是集成电路的两个分开的层。 掩模包括对第一波长的光和第二波长的光完全透射的掩模基板。 第一材料层设置在掩模基板上，其中第一材料对于第一波长的光是基本上不透明的。 第一材料的层被图案化为第一层。 第二材料层设置在掩模基板上，其中第二材料对第二波长的光基本上是不透明的。 第二材料的层被图案化为第二层，其中第一材料的层和第二材料的层在掩模衬底上对准，用于正确对准处理衬底上的第一和第二层。

公开(公告)号：US06818365B2

公开(公告)日：2004-11-16

申请号：US10295489

申请日：2002-11-15

申请人： Duane B. Barber

发明人： Duane B. Barber

IPC分类号： G03F900

CPC分类号： G03F9/7034

摘要： A method for leveling an exposure field of view at a peripheral edge of a substrate. The field of view is aligned to a first position at the peripheral edge of the substrate, where the field of view has an inner edge and an outer edge, relative to the peripheral edge of the substrate. Whole device patterns within the field of view are identified, and the alignment of the field of view is altered to a second position so as to place the outer edge of the field of view adjacent the whole device patterns within the field of view. Level measurement information from the field of view at the second position is acquired and stored. The field of view is realigned to the first position, and the substrate is leveled within the field of view at the first position using the level measurement information acquired from the field of view at the second position.

公开(公告)号：US08685822B2

公开(公告)日：2014-04-01

申请号：US13022628

申请日：2011-02-07

申请人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

发明人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

IPC分类号： H01L21/336

CPC分类号： H01L29/66727 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

摘要翻译： 包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。 半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。 在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。 屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。 在器件区域中的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。 器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。 器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

公开(公告)号：US07897462B2

公开(公告)日：2011-03-01

申请号：US12271083

申请日：2008-11-14

申请人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

发明人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

IPC分类号： H01L21/336

CPC分类号： H01L29/66727 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

摘要翻译： 包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。 半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。 在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。 屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。 在器件区域中的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。 器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。 器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。