公开(公告)号：US07638245B2

公开(公告)日：2009-12-29

申请号：US12167381

申请日：2008-07-03

申请人： David J. Sturtevant ,  Duane B. Barber ,  Ann I. Kang

发明人： David J. Sturtevant ,  Duane B. Barber ,  Ann I. Kang

IPC分类号： G03F1/00 ,  G03F1/14

CPC分类号： G03F7/70433 ,  G03F1/00 ,  G03F1/50 ,  G03F7/70466

摘要： A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third layer pattern is formed on the second mask.

摘要翻译： 根据第一设计制造集成电路的方法。 第一种设计是第一种模式，第一种模式是第一种设计所独有的。 使用在其上的块中形成有第一图案的第一掩模对第一图案成像。 在第一掩模上不形成第一和第二设计的其它图案。 使用在其上的块中形成有第二图案的第二掩模将第二图案成像在基板上。 在第二掩模上形成至少一个第三层图案。

公开(公告)号：US07550236B2

公开(公告)日：2009-06-23

申请号：US10953322

申请日：2004-09-29

申请人： Duane B. Barber ,  Phong T Do ,  Douglas M. Horn

发明人： Duane B. Barber ,  Phong T Do ,  Douglas M. Horn

IPC分类号： G03F1/00 ,  G03F1/14

CPC分类号： G03F1/50

摘要： A mask for exposing a first layer and a second layer on a process substrate, where the first and second layers are two separate layers of an integrated circuit. The mask includes a mask substrate that is substantially completely transmissive to a first wavelength of light and a second wavelength of light. A layer of a first material is disposed on the mask substrate, where the first material is substantially opaque to the first wavelength of light. The layer of the first material is patterned for the first layer. A layer of a second material is disposed on the mask substrate, where the second material is substantially opaque to the second wavelength of light. The layer of the second material is patterned for the second layer, where the layer of the first material and the layer of the second material are aligned on the mask substrate for proper alignment of the first and second layers on the process substrate.

摘要翻译： 用于在处理衬底上暴露第一层和第二层的掩模，其中第一层和第二层是集成电路的两个分开的层。 掩模包括对第一波长的光和第二波长的光完全透射的掩模基板。 第一材料层设置在掩模基板上，其中第一材料对于第一波长的光是基本上不透明的。 第一材料的层被图案化为第一层。 第二材料层设置在掩模基板上，其中第二材料对第二波长的光基本上是不透明的。 第二材料的层被图案化为第二层，其中第一材料的层和第二材料的层在掩模衬底上对准，用于正确对准处理衬底上的第一和第二层。

公开(公告)号：US06818365B2

公开(公告)日：2004-11-16

申请号：US10295489

申请日：2002-11-15

申请人： Duane B. Barber

发明人： Duane B. Barber

IPC分类号： G03F900

CPC分类号： G03F9/7034

摘要： A method for leveling an exposure field of view at a peripheral edge of a substrate. The field of view is aligned to a first position at the peripheral edge of the substrate, where the field of view has an inner edge and an outer edge, relative to the peripheral edge of the substrate. Whole device patterns within the field of view are identified, and the alignment of the field of view is altered to a second position so as to place the outer edge of the field of view adjacent the whole device patterns within the field of view. Level measurement information from the field of view at the second position is acquired and stored. The field of view is realigned to the first position, and the substrate is leveled within the field of view at the first position using the level measurement information acquired from the field of view at the second position.

公开(公告)号：US08685633B2

公开(公告)日：2014-04-01

申请号：US10929706

申请日：2004-08-30

申请人： Duane B. Barber ,  David J. Sturtevant

发明人： Duane B. Barber ,  David J. Sturtevant

IPC分类号： G03F1/00

CPC分类号： G03F7/70466 ,  G03F7/70425

摘要： A method of printing an image on a wafer. The method includes the steps of printing a main image, wherein the main image includes fields which are fully on the wafer, and printing an alternate image, wherein the alternate image includes fields which are only partially on the wafer. The alternate image could be placed on a separate mask which is loaded onto the exposure tool after the mask with the main image has completed printing. Alternatively, it could be an extra image specially inserted on the mask with the main image for that layer.

摘要翻译： 一种在晶片上打印图像的方法。 该方法包括打印主图像的步骤，其中主图像包括完全在晶片上的场，以及打印替代图像，其中替代图像包括仅部分地在晶片上的场。 替代图像可以被放置在单独的掩模上，其中主图像的掩模已经完成打印之后被加载到曝光工具上。 或者，它可以是特别插入到掩模上的额外的图像，该图像的主图像。

公开(公告)号：US20100123193A1

公开(公告)日：2010-05-20

申请号：US12271092

申请日：2008-11-14

申请人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

发明人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L27/088 ,  H01L21/823487

摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

摘要翻译： 包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。 半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。 在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。 屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。 在器件区域的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。 器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。 器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

公开(公告)号：US07018753B2

公开(公告)日：2006-03-28

申请号：US10429376

申请日：2003-05-05

申请人： David J. Sturtevant ,  Duane B. Barber ,  Ann I. Kang

发明人： David J. Sturtevant ,  Duane B. Barber ,  Ann I. Kang

IPC分类号： G03F9/00 ,  G03F7/20 ,  G03F7/22

CPC分类号： G03F7/70433 ,  G03F1/00 ,  G03F1/50 ,  G03F7/70466

摘要： A method of fabricating integrated circuits according to a first design by imaging a first layer on a substrate using a first mask having a block of first patterns in common with a second design, but without any other patterns of the first or second designs and imaging a second layer on the substrate using a second mask having a block of second patterns unique to the first design and at least one third layer pattern. The block of first patterns is repeatedly exposed in a first grid and the block of second patterns is repeatedly exposed in a second grid, each without overlap in the corresponding layer. The grids are aligned such that the integrated circuits and test structures in scribe lines between the integrated circuits are properly formed on the substrate. The first patterns can be for large fields and the second patterns can be for small fields.

摘要翻译： 一种根据第一设计制造集成电路的方法，其通过使用具有与第二设计相同的第一图案块的第一掩模成像基板上的第一层，但是没有第一或第二设计和成像的任何其它图案 第二层，使用具有第一图案独特的第二图案的块和至少一个第三图案的第二掩模。 第一图案的块在第一栅格中重复曝光，并且第二图案的块在第二栅格中重复地暴露，每个在相应层中不重叠。 栅格对齐，使得在集成电路之间的划线中的集成电路和测试结构适当地形成在衬底上。 第一种模式可以用于大字段，第二种模式可以用于小字段。

公开(公告)号：US06861183B2

公开(公告)日：2005-03-01

申请号：US10293458

申请日：2002-11-13

申请人： Duane B. Barber

发明人： Duane B. Barber

IPC分类号： G03C5/00 ,  G03F1/00 ,  G03F1/36 ,  G03F9/00

CPC分类号： G03F1/36

摘要： A mask used for imaging nearly dense features in a substrate. Scatter dots are disposed on the mask in proximity to the nearly dense features, where the scatter dots adjust photon levels of the nearly dense features to a desired level. The adjustment is controlled by selective adjustment of a duty cycle and degree of stagger of the scatter dots. In this manner, the scatter dots adjust the optical properties of the nearly dense features to be very similar to the optical properties of dense features, which enables more accurate imaging of the nearly dense features on the substrate. However, because the scatter dots are discontinuous, they do not overcorrect in the same manner that a scatter bar formed at a minimum resolution might overcorrect. Further, there is a reduced likelihood that the scatter dots would actually print on the substrate.

摘要翻译： 用于在基底中成像几乎致密特征的掩模。 散射点在几乎致密的特征附近设置在掩模上，其中散射点将几乎致密特征的光子水平调整到期望的水平。 通过选择性调整占空比和散点的交错程度来控制调整。 以这种方式，散射点将几乎致密特征的光学特性调整为非常类似于致密特征的光学性质，这使得能够对基底上几乎致密的特征进行更精确的成像。 然而，由于散射点是不连续的，它们不会以以最小分辨率形成的散射条可能过度校正的相同方式过度校正。 此外，散射点实际上可能在基板上打印的可能性降低。

公开(公告)号：US5825105A

公开(公告)日：1998-10-20

申请号：US835220

申请日：1997-04-07

申请人： John B. Barber ,  Duane B. Barber

发明人： John B. Barber ,  Duane B. Barber

IPC分类号： B60L13/10 ,  H01L21/677 ,  H02N15/00 ,  H02K41/00

CPC分类号： H02N15/00 ,  B60L13/10

摘要： A system of supporting useful payloads via magnetic forces using magnets of unmodulated strength operating in attractive mode without the necessity of complex sensing and control for maintaining a payload lift. Disclosed are embodiments of or lifting, conveying, and/or transporting of loads including various features for enhancing performance and stability thereof.

摘要翻译： 一种通过磁力支持有用有效载荷的系统，其使用在有吸引力的模式下操作的未调制强度的磁体，而不需要用于维持有效载荷提升的复杂的感测和控制。 公开了包括用于增强其性能和稳定性的各种特征的负载的实施例或提升，输送和/或运输负载。

公开(公告)号：US20110127603A1

公开(公告)日：2011-06-02

申请号：US13022628

申请日：2011-02-07

申请人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

发明人： Peter A. Burke ,  Duane B. Barber ,  Brian Pratt

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66727 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

摘要翻译： 包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。 半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。 在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。 屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。 在器件区域中的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。 器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。 器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

公开(公告)号：US20080274417A1

公开(公告)日：2008-11-06

申请号：US12167381

申请日：2008-07-03

申请人： David J. Sturtevant ,  Duane B. Barber ,  Ann I. Kang

发明人： David J. Sturtevant ,  Duane B. Barber ,  Ann I. Kang

IPC分类号： G03F1/00

CPC分类号： G03F7/70433 ,  G03F1/00 ,  G03F1/50 ,  G03F7/70466

摘要： A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third layer pattern is formed on the second mask.

摘要翻译： 根据第一设计制造集成电路的方法。 第一种设计是第一种模式，第一种模式是第一种设计所独有的。 使用在其上的块中形成有第一图案的第一掩模对第一图案成像。 在第一掩模上不形成第一和第二设计的其它图案。 使用在其上的块中形成有第二图案的第二掩模将第二图案成像在基板上。 在第二掩模上形成至少一个第三层图案。