公开(公告)号：US12130773B2

公开(公告)日：2024-10-29

申请号：US18084266

申请日：2022-12-19

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar Rangarajan ,  Varun Jindal

IPC: G06F12/08 ,  G06F12/0875 ,  G06F15/78

CPC classification number: G06F15/7814 ,  G06F12/0875 ,  G06F2212/452

Abstract: Aspects of the disclosure are directed to a quality of service (QOS) assignment policy for processor applications in a system on a chip (SoC). In accordance with one aspect, the system on a chip (SoC) includes an applications central processing unit (CPU), wherein the applications CPU comprises a quality of service (QOS) database table configured to list a plurality of QoS metrics associated with a plurality of processor threads, wherein at least one of the plurality of QoS metrics is used to determine a dynamic clock and voltage scaling (DCVS) operating point; a graphics processing unit (GPU) coupled to the applications CPU; and a common interconnection databus coupled to the applications CPU and the GPU.

公开(公告)号：US11630694B2

公开(公告)日：2023-04-18

申请号：US17148314

申请日：2021-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Vijayakumar Ashok Dibbad ,  Bharat Kumar Rangarajan ,  Prashanth Kumar Kakkireni ,  Srinivas Turaga

IPC: G06F9/46 ,  G06F9/48 ,  G06F1/28 ,  G06F9/52

Abstract: Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.

公开(公告)号：US11493986B2

公开(公告)日：2022-11-08

申请号：US16724317

申请日：2019-12-22

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar Rangarajan ,  Rajesh Arimilli ,  Srinivas Turaga

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3293 ,  G06F1/3296

Abstract: Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.

公开(公告)号：US11169593B2

公开(公告)日：2021-11-09

申请号：US15929732

申请日：2020-05-19

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra Srinivas ,  Bharat Kumar Rangarajan ,  Rajesh Arimilli

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G11C5/14 ,  G06F1/3206 ,  G06F1/26

Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

公开(公告)号：US10466766B2

公开(公告)日：2019-11-05

申请号：US15808538

申请日：2017-11-09

Applicant: QUALCOMM Incorporated

Inventor： Rajesh Arimilli ,  Bharat Kumar Rangarajan ,  Rakesh Misra

IPC: G11C5/14 ,  G06F1/3234 ,  G06F1/3287 ,  G11C11/419 ,  G06F13/42 ,  G06F1/3206

Abstract: Systems, methods, and apparatus for operating a central processing unit (CPU) are provided. The CPU includes a plurality of memories including a first group of memories and a second group of memories. The plurality of memories are grouped based on a timing criticality of each memory. The CPU further includes a memory core (MX) voltage supply configured to provide the plurality of memories with an MX voltage, an application processor core (APC) voltage supply configured to provide the plurality of memories with an APC voltage, and a voltage switching circuit. The voltage switching circuit detects an operating mode of the CPU and switches a voltage provided to at least one of the first group of memories or the second group of memories between the MX voltage and the APC voltage based on a type of the operating mode detected.