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公开(公告)号：US20160233763A1
公开(公告)日：2016-08-11
申请号：US14617025
申请日：2015-02-09
Applicant: QUALCOMM Incorporated
Inventor： Dongmin Park , Lai Kan Leung , Jong Min Park
CPC classification number: H02M3/07 , H03L7/0895 , H03L7/093 , H03L7/099
Abstract: An apparatus including: a current source configured to generate current; a bias node coupled to the current source; a switching current source circuit coupled to the current source and the bias node to allow the current to flow through the switching current source circuit into the bias node; a biasing circuit configured to receive a control signal from a phase detector, and mirror the current flowing through the switching current source circuit in response to the control signal; and a switch device disposed between the switching current source circuit and the biasing circuit to isolate the switching current source circuit from the biasing circuit.
Abstract translation: 一种装置，包括：被配置为产生电流的电流源; 耦合到所述电流源的偏置节点; 开关电流源电路，耦合到电流源和偏置节点，以允许电流流过开关电流源电路进入偏置节点; 偏置电路，被配置为从相位检测器接收控制信号，并响应于控制信号反射流过开关电流源电路的电流; 以及设置在开关电流源电路和偏置电路之间以将开关电流源电路与偏置电路隔离的开关装置。
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公开(公告)号：US11342927B1
公开(公告)日：2022-05-24
申请号：US17361217
申请日：2021-06-28
Applicant: QUALCOMM Incorporated
Inventor： Younghyun Lim , Yiwu Tang , Dongmin Park , Yunliang Zhu , Mustafa Keskin , Yue Chao
Abstract: Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.
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公开(公告)号：US11277140B1
公开(公告)日：2022-03-15
申请号：US17340914
申请日：2021-06-07
Applicant: QUALCOMM Incorporated
Inventor： Dongmin Park , Alvin Siu-Chi Li , Masoud Moslehi Bajestan , Yiwu Tang
Abstract: In certain aspects, a sampler includes a sampling capacitor, a precharge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference-voltage circuit coupled to the sampling capacitor. The reference-voltage circuit is configured to generate a reference voltage based on a supply voltage, and generate a voltage difference between a voltage on the sampling capacitor and the reference voltage.
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公开(公告)号：US11271574B1
公开(公告)日：2022-03-08
申请号：US17197827
申请日：2021-03-10
Applicant: QUALCOMM INCORPORATED
Inventor： Tomas O'Sullivan , Lai Kan Leung , Dongling Pan , Jianjun Yu , Dongmin Park
Abstract: A frequency synthesizer system may include a first voltage-controlled oscillator (VCO) circuit, a second VCO circuit, and multiplexing circuitry. The multiplexing circuitry may be configured to select either the output of the first VCO circuit or the output of the second VCO circuit in response to a mode selection signal.
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Patent Agency Ranking
公开(公告)号：US11264995B1
公开(公告)日：2022-03-01
申请号：US17079795
申请日：2020-10-26
Applicant: QUALCOMM INCORPORATED
Inventor： Yue Chao , Yiwu Tang , Yunliang Zhu , Dongmin Park , Jingcheng Zhuang
Abstract: A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal.
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公开(公告)号：US20180138822A1
公开(公告)日：2018-05-17
申请号：US15349432
申请日：2016-11-11
Applicant: QUALCOMM Incorporated
Inventor： Dongmin Park , Jong Min Park , Lai Kan Leung
IPC: H02M7/217
Abstract: A method and system for self-powering a clock input buffer is disclosed. The system includes an input node adapted to receive an alternating current (AC) signal having an instantaneous voltage oscillating between a minimum voltage and a maximum voltage. The system includes a pass transistor having a voltage controlled terminal, a first transfer terminal, and a second transfer terminal. The first transfer terminal connects to the input node and the second transfer terminal connects to a power node. The circuit also includes a plurality of transistors adapted to form a logic gate connected to the power node, and having a sensing terminal connected to the input node and an output terminal connected to the voltage controlled terminal. The logic gate produces a control voltage on the output terminal in response to an input voltage on the sensing terminal. The circuit also includes an energy-storage element having a first terminal connected to the power node.
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公开(公告)号：US20180062655A1
公开(公告)日：2018-03-01
申请号：US15253683
申请日：2016-08-31
Applicant: QUALCOMM Incorporated
Inventor： Dongmin Park , Jong Min Park , Lai Kan Leung
IPC: H03K19/0185
CPC classification number: H03K19/018507 , H03K3/356104 , H03K3/356113
Abstract: A level-shifter is provided in which the devices may all be sized approximately the same yet a known startup state is provided at power-up by forming the level-shifter using a one-sided NMOS latch. The one-sided NMOS latch is powered through a pair of head-switch transistors. A pair of pull-down transistors function to flip a binary state for the one-sided NMOS latch.
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公开(公告)号：US09490696B2
公开(公告)日：2016-11-08
申请号：US14617025
申请日：2015-02-09
Applicant: QUALCOMM Incorporated
Inventor： Dongmin Park , Lai Kan Leung , Jong Min Park
CPC classification number: H02M3/07 , H03L7/0895 , H03L7/093 , H03L7/099
Abstract: An apparatus including: a current source configured to generate current; a bias node coupled to the current source; a switching current source circuit coupled to the current source and the bias node to allow the current to flow through the switching current source circuit into the bias node; a biasing circuit configured to receive a control signal from a phase detector, and mirror the current flowing through the switching current source circuit in response to the control signal; and a switch device disposed between the switching current source circuit and the biasing circuit to isolate the switching current source circuit from the biasing circuit.
Abstract translation: 一种装置，包括：被配置为产生电流的电流源; 耦合到所述电流源的偏置节点; 开关电流源电路，耦合到电流源和偏置节点，以允许电流流过开关电流源电路进入偏置节点; 偏置电路，被配置为从相位检测器接收控制信号，并响应于控制信号反射流过开关电流源电路的电流; 以及设置在开关电流源电路和偏置电路之间以将开关电流源电路与偏置电路隔离的开关装置。
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公开(公告)号：US20160233764A1
公开(公告)日：2016-08-11
申请号：US14618369
申请日：2015-02-10
Applicant: QUALCOMM Incorporated
Inventor： Dongmin Park , Lai Kan Leung , Jong Min Park
CPC classification number: H02M3/07 , H03L7/08 , H03L7/0895
Abstract: An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.
Abstract translation: 一种装置，包括：被配置为产生电流的电流源; 耦合到电流源的开关电流源电路和第一偏置节点，以允许电流流过开关电流源电路进入第一偏置节点; 第一偏置电路，被配置为从相位检测器接收第一控制信号，所述第一偏置电路被配置为响应于所述第一控制信号镜像流过所述开关电流源电路的电流; 第二偏置电路，耦合到输出节点处的第一偏置电路和第二偏置节点，第二偏置电路被配置为从相位检测器接收第二控制信号; 以及跨导放大器，被配置为从所述输出节点接收反馈信号并产生输出电流以控制所述第二偏置节点。
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