公开(公告)号：US11984900B2

公开(公告)日：2024-05-14

申请号：US17934654

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Jianjun Yu ,  Yue Chao ,  Tomas O'Sullivan ,  Lai Kan Leung

IPC: H03L7/099 ,  H03B5/12 ,  H03K3/0231 ,  H03M1/46

CPC classification number: H03L7/099 ,  H03B5/1293 ,  H03K3/0231 ,  H03M1/46

Abstract: Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An example PLL circuit includes a charge pump, a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node, and a tracking circuit coupled to the node. The tracking circuit is generally configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.

公开(公告)号：US11271574B1

公开(公告)日：2022-03-08

申请号：US17197827

申请日：2021-03-10

Applicant: QUALCOMM INCORPORATED

Inventor： Tomas O'Sullivan ,  Lai Kan Leung ,  Dongling Pan ,  Jianjun Yu ,  Dongmin Park

IPC: H03L7/185 ,  H03L7/099

Abstract: A frequency synthesizer system may include a first voltage-controlled oscillator (VCO) circuit, a second VCO circuit, and multiplexing circuitry. The multiplexing circuitry may be configured to select either the output of the first VCO circuit or the output of the second VCO circuit in response to a mode selection signal.

公开(公告)号：US11632230B2

公开(公告)日：2023-04-18

申请号：US17340953

申请日：2021-06-07

Applicant: QUALCOMM Incorporated

Inventor： Alvin Siu-Chi Li ,  Tomas O'Sullivan ,  Jianjun Yu ,  Yiwu Tang

IPC: H04L7/033 ,  H03L7/08 ,  H03L7/085 ,  H03K5/131

Abstract: An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.

公开(公告)号：US11387833B1

公开(公告)日：2022-07-12

申请号：US17466901

申请日：2021-09-03

Applicant: QUALCOMM Incorporated

Inventor： Alvin Siu-Chi Li ,  Yue Chao ,  Dongmin Park ,  Heui In Yoon ,  Tomas O'Sullivan ,  Jianjun Yu ,  Yiwu Tang

IPC: H03L7/089 ,  G04F10/00 ,  H04L7/033

Abstract: A method of quantization noise cancellation in a phase-locked loop (PLL) is provided according to certain aspects. The PLL includes a phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal. The method includes delaying the reference signal by a first time delay, delaying the feedback signal by a second time delay, receiving a delta-sigma modulator (DSM) error signal, and adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal.