公开(公告)号：US09189438B2

公开(公告)日：2015-11-17

申请号：US13799286

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Venugopal Boynapalli ,  Kevin Robert Bowles ,  Vijay Bantval

IPC: G06F13/40

CPC classification number: G06F13/40 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture.

Abstract translation: 总线通信架构中的动态功率降低的各个方面在本文中被描述为体现在XBAR架构中，其提供多路径和中继器电路的灵活门控，以允许多个所选择的客户端中的任何一个与任何其他互连的客户端通信，同时减少 通过禁用总线通信架构中的未使用的中继器电路来实现动态功耗。

公开(公告)号：US09081060B2

公开(公告)日：2015-07-14

申请号：US14046084

申请日：2013-10-04

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Venkatasubramanian Narayanan ,  Venugopal Boynapalli ,  Sagar Suresh Sabade ,  Bilal Zafar

IPC: G01R31/3177 ,  G01R31/3185 ,  G06F11/27 ,  G01R31/3187

CPC classification number: G01R31/3177 ,  G01R31/3185 ,  G01R31/318516 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/022 ,  G11C29/12

Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

Abstract translation: 提供了可重构指令单元阵列（RICA），其包括多个主开关盒，其被配置为通过交叉开关从多个缓冲器读取和写入。 主内置自检（MBIST）引擎被配置为将测试字驱动到至少一个主开关盒的写入路径中并且控制交叉开关，使得驱动的测试字广播到所有 用于存储的缓冲区 MBIST引擎还被配置为通过交叉开关中的读总线从缓冲器中检索存储的测试字。

公开(公告)号：US08860457B2

公开(公告)日：2014-10-14

申请号：US13784827

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Sami Khawam ,  Ioannis Nousias ,  Raghavan Thirumala

IPC: H03K19/177 ,  G06F15/80

CPC classification number: G06F15/80 ,  G06F15/7871

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.

Abstract translation: 可重构指令单元阵列（RICA）包括多个开关盒。 每个开关盒包括根据存储在开关盒的锁存器阵列中的配置字来配置的指令单元和交换结构。 开关盒被布置成广播组，使得每个广播组中的锁存器阵列并行地接收配置字。

公开(公告)号：US20140281112A1

公开(公告)日：2014-09-18

申请号：US13799286

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Hari Rao ,  Venugopal Boynapalli ,  Kevin Robert Bowles ,  Vijay Bantval

IPC: G06F13/40

CPC classification number: G06F13/40 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture.

Abstract translation: 总线通信架构中的动态功率降低的各个方面在本文中被描述为体现在XBAR架构中，其提供多路径和中继器电路的灵活门控，以允许多个所选择的客户端中的任何一个与任何其他互连的客户端通信，同时减少 通过禁用总线通信架构中的未使用的中继器电路来实现动态功耗。

公开(公告)号：US10658029B2

公开(公告)日：2020-05-19

申请号：US16138174

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Hoan Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  Hari Rao

IPC: G11C11/4091 ,  G11C7/06 ,  G11C11/419 ,  G11C11/408 ,  G11C8/08 ,  G11C8/10 ,  G11C16/26

Abstract: Certain aspects of the present disclosure provide apparatus and methods for performing memory read operations. One example method generally includes precharging a plurality of memory columns during a precharging phase of a read access cycle. The method also includes sensing first data stored in a first memory cell of a first memory column of the plurality of memory columns during a memory read phase of the read access cycle, and sensing second data stored in a second memory cell of a second memory column of the plurality of memory columns during the same memory read phase of the read access cycle.

公开(公告)号：US09330040B2

公开(公告)日：2016-05-03

申请号：US14025646

申请日：2013-09-12

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Ioannis Nousias ,  Sami Khawam

IPC: G06F3/00 ,  G06F13/28 ,  G06F13/00 ,  G06F13/40 ,  G06F12/12 ,  G06F1/16 ,  G06F15/80 ,  G06F1/08 ,  H03K19/177

CPC classification number: G06F13/4022 ,  G06F1/08 ,  G06F1/1615 ,  G06F12/125 ,  G06F15/80 ,  H03K19/17756 ,  H03K19/1776

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in each switch box. The switch boxes are arranged into serial loading sets such that the switch boxes in each serial loading set are configured to form a multi-bit shift register chain for serial shifting the corresponding configuration words.

Abstract translation: 可重构指令单元阵列（RICA）包括多个开关盒。 每个开关盒包括根据存储在每个开关盒中的配置字来配置的指令单元和交换结构。 开关盒被布置成串行加载集合，使得每个串行加载集合中的开关盒被配置为形成用于串行移位相应配置字的多位移位寄存器链。