公开(公告)号：US20240378166A1

公开(公告)日：2024-11-14

申请号：US18314676

申请日：2023-05-09

Applicant: QUALCOMM INCORPORATED

Inventor： Madhu Yashwanth BOENAPALLI ,  Kaustub Naidu PAILA RAM ,  Sravani DEVINENI ,  Sai Praneeth SREERAM ,  Vinod KUMAR KURUMA ,  Rajendra Varma PUSAPATI ,  Surendra PARAVADA

IPC: G06F13/42

Abstract: A Peripheral Component Interconnect Express (PCIe) system is configured to determine when the frequency of link speed switching needed to service incoming and upcoming client requests is too high. The system is also configured to determine a modest link speed to be used to service incoming and upcoming client requests in cases where the link speed switching that will be needed is too high and causes the incoming and upcoming client requests to be serviced at the modest link speed instead of at the link speeds associated with the predefined BWs of the clients. By doing this when the frequency of link speed switching needed is too high, the PCIe system achieves better throughput while also reducing power consumption.

公开(公告)号：US20240319913A1

公开(公告)日：2024-09-26

申请号：US18189141

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Sonali JABREVA ,  Prakhar SRIVASTAVA ,  Surendra PARAVADA ,  Yogananda Rao CHILLARIGA ,  Madhu Yashwanth BOENAPALLI

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0604

Abstract: Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the write throughout of a data storage device. In some aspects, the storage device can be provided with multiple write buffers to improve write throughput. In some aspects, the data storage device can continue to handle commands using a command queue while performing a write buffer flush operation. Therefore, the data storage device can avoid suspending the write buffer flush operation when a new command is received by the command queue. In some aspects, the storage device can perform a write buffer flush operation when a command queue is not empty.

公开(公告)号：US20210109674A1

公开(公告)日：2021-04-15

申请号：US16653931

申请日：2019-10-15

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA ,  Venu Madhav MOKKAPATI ,  Sai Praneeth SREERAM

IPC: G06F3/06

Abstract: In some aspects, the present disclosure provides a method for managing memory commands from a plurality of masters. The method includes receiving, at a storage driver, a plurality of memory commands from the plurality of masters and determining, by the storage driver, a number of command queues of a plurality of command queues to use to service the plurality of memory commands. In certain aspects, the method includes routing, via one or more of a plurality of lanes, the plurality of memory commands to a storage controller according to the determined number of command queues, wherein each of the plurality of lanes corresponds to one of the plurality of command queues and storing, by the storage controller, one or more of the plurality of memory commands in each of the determined number of command queues.

公开(公告)号：US20200233605A1

公开(公告)日：2020-07-23

申请号：US16255477

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Hyunsuk SHIN ,  Surendra PARAVADA ,  Sai Praneeth SREERAM ,  Venu Madhav MOKKAPATI

IPC: G06F3/06

Abstract: A method of scheduling universal flash storage (UFS) operations using a refresh handover mechanism is described. The method includes receiving, during refresh of a UFS device, a request for an input/output (I/O) operation. The method also includes handing over between a first type of refresh operation and a second type of refresh operation in response to the request for the I/O operation.

公开(公告)号：US20190304552A1

公开(公告)日：2019-10-03

申请号：US15942380

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA ,  Sai Praneeth SREERAM ,  Venu Madhav MOKKAPATI

IPC: G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G11C16/32 ,  G06F3/06

Abstract: An embodiment is directed to an apparatus that comprises a host controller and a flash memory. The host controller monitors a temperature in a first memory block of the flash memory (e.g., based on a reported temperature measurements from the flash memory), and selectively synchronizes a first refresh of the first memory block with a second refresh of a second memory block of the flash memory based in part upon the monitored temperature. For example, an immediate refresh of the first memory block may be performed if there is a pending I/O request for the first memory block, an error rate associated with the first memory block exceeds an error rate threshold and/or the monitored temperature of the first memory block exceeds a temperature threshold; otherwise, a synchronized refresh of the first and second memory blocks may be executed.

公开(公告)号：US20250103232A1

公开(公告)日：2025-03-27

申请号：US18472959

申请日：2023-09-22

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Sai Praneeth SREERAM ,  Surendra PARAVADA

IPC: G06F3/06

Abstract: A host device includes a memory configured to store a logical-to-physical address mapping table of a flash memory device. The host device also includes one or more processors coupled to the memory and configured to be coupled to the flash memory device. The one or more processors are configured to determine whether a trigger condition is satisfied. The trigger condition is associated with checking a distribution of write data that is written to the flash memory device. The one or more processors are also configured to, based on a determination that the trigger condition is satisfied, identify a die of the flash memory device that has a higher data occupancy than at least one other die of the flash memory device, and send a command to the flash memory device to move data from the identified die to one or more other dies of the flash memory device.

公开(公告)号：US20250086037A1

公开(公告)日：2025-03-13

申请号：US18466186

申请日：2023-09-13

Applicant: QUALCOMM INCORPORATED

Inventor： Anirudh K ,  Madhu Yashwanth BOENAPALLI ,  Sai Praneeth SREERAM ,  Surendra PARAVADA ,  Venugopala Rao GUJJA

IPC: G06F11/07 ,  G06F11/14

Abstract: A system and method reduce bootup latency in systems that run Auto operating systems (Auto OS). When, or just prior to, the system controller initiating suspend-to-disk (S2D) process entry, the system controller causes a memory controller to determine the percentage of volatile memory that is currently occupied and compares that percentage of occupancy to a predetermined threshold (TH) percentage. If the percentage of occupancy exceeds the predetermined TH percentage, then the memory controller tags apps that are occupying volatile memory as either background apps or foreground apps, terminates the background apps, clears volatile memory of any instructions and data associated with the terminated background apps, takes a snapshot of the state of volatile memory after the terminated background apps and associated data have been cleared, and saves the snapshot to a designated storage location in nonvolatile memory before entering hibernate mode.

公开(公告)号：US20240427714A1

公开(公告)日：2024-12-26

申请号：US18338070

申请日：2023-06-20

Applicant: QUALCOMM INCORPORATED

Inventor： Surendra PARAVADA ,  Madhu Yashwanth BOENAPALLI ,  Vinod Kumar KURUMA ,  Sai Praneeth SREERAM ,  Ravindranath DODDI

IPC: G06F13/16

Abstract: A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced latency and improved performance by reconfiguring the PCIe link to use an increased number of lanes for retransmitting data packets held in a replay buffer if one or more data packets transmitted by the TX device are flagged as not acknowledged (NACK) by the RX device. Before retransmitting the NACK-flagged packet(s), the link is reconfigured to use a greater number of lanes, preferably the maximum number of lanes that are available for use, and then the NACK-flagged packet(s) is retransmitted using the greater number of lanes until successful receipt of the NACK-flagged packets has been acknowledged by the RX device. Once the NACK-flagged packet(s) is successfully received by the RX device, the link is reconfigured to use the previous number of lanes and operations of the link resume using the previous number of lanes.

公开(公告)号：US20210294654A1

公开(公告)日：2021-09-23

申请号：US16824338

申请日：2020-03-19

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA ,  Sai Praneeth SREERAM

IPC: G06F9/50 ,  G06F9/54 ,  G06F9/30 ,  G06F9/46 ,  G06F11/34 ,  G06F12/02 ,  G06F12/123

Abstract: A method of shuffling turbo-write buffers of a universal flash storage system is described. The method includes periodically determining a performance index of each turbo-write buffer allocated to a unique logical unit number of the universal flash storage system. The method also includes shifting a position of at least two of the turbo-write buffers according to the performance index of each of the turbo-write buffers and a threshold performance level.

公开(公告)号：US20210117127A1

公开(公告)日：2021-04-22

申请号：US16655014

申请日：2019-10-16

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Sai Praneeth SREERAM ,  Surendra PARAVADA ,  Venu Madhav MOKKAPATI

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes receiving, by a host controller, a plurality of memory commands from a UFS driver, storing, by the host controller, the plurality of memory commands in a command queue, and determining, by the host controller, whether the plurality of memory commands comprises a contiguous set of commands, where a number of the contiguous set of commands is greater than a threshold number of commands, and where each command of the contiguous set of commands has a priority less than a threshold priority.