公开(公告)号：US20240419613A1

公开(公告)日：2024-12-19

申请号：US18337235

申请日：2023-06-19

Applicant: QUALCOMM INCORPORATED

Inventor： Madhu Yashwanth BOENAPALLI ,  Ravindranath DODDI ,  Vinod Kumar KURUMA ,  Surendra PARAVADA ,  Sai Praneeth SREERAM

IPC: G06F13/16

Abstract: A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced power consumption and latency. When the link transitions from an active functional state in which the link has a first configuration of N active lanes to a power-saving state, the number of active lanes is collapsed such that M of the N lanes are maintained in an active power-saving state and P of the N lanes are maintained in an electrically idle state, where M, N and P are positive integers and N>P>M. The reduction in lane width reduces power consumption. Bit values specifying the current link configuration can be saved in a control register and read and compared to bit values contained in a link control register before transitioning back to the active functional state. If the bit values match, the active functional state is resumed directly from the recovery state, thereby reducing latency.

公开(公告)号：US20240160576A1

公开(公告)日：2024-05-16

申请号：US18054249

申请日：2022-11-10

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA ,  Sai Praneeth SREERAM

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/1028 ,  G06F2212/655

Abstract: Methods that may be performed by a host controller of a computing device for synchronizing logical-to-physical (L2P) tables before entering a hibernate mode are disclosed. Embodiment methods may include determining whether a first L2P table stored in a dynamic random-access memory (DRAM) communicatively connected to the host controller is out of synchronization with a second L2P table stored in a static random-access memory (SRAM) of a universal flash storage (UFS) device communicatively connected to the host controller via a link. If the first and second L2P tables are out of synch, the host controller may retrieve at least one modified L2P map entry from the second L2P table when the UFS device is configured to enter a hibernate mode from the UFS device, and update the first L2P tabled with the at least one modified L2P map entry before the link and the UFS device enter the hibernate mode.

公开(公告)号：US20240345762A1

公开(公告)日：2024-10-17

申请号：US18298484

申请日：2023-04-11

Applicant: QUALCOMM Incorporated

Inventor： Sravani DEVINENI ,  Sai Praneeth SREERAM ,  Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for updating logical-to-physical (L2P) address mapping tables. Various embodiments may include enabling a device control mode (DCM) of host performance booster (HPB) based on a flush of a writebooster buffer to a normal storage of a UFS device of the UFS system, and updating an L2P address mapping table at a host device of the UFS system while DCM is enabled based on the flush of the writebooster buffer to the normal storage. Some embodiments may include generating a signal having an indicator of a UFS protocol information unit configured to indicate a change in an HPB mode at the UFS device based on the flush of the writebooster buffer to the normal storage, and sending the signal from the UFS device to the host device.

公开(公告)号：US20240184711A1

公开(公告)日：2024-06-06

申请号：US18061451

申请日：2022-12-03

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA ,  Sai Praneeth SREERAM

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/1016

Abstract: Methods that may be performed by a host controller of a computing device for host performance booster (HPB) mode management. Embodiments may include enabling an HPB mode based on availability of the host controller and availability of a memory device controller. In some embodiments, enabling the HPB mode based on the availability of the host controller and the availability of the memory device controller may include enabling a device control mode in response to an operating state of the host controller being busy and an operating state of the memory device controller being available. In some embodiments, enabling the HPB mode based on the availability of the host controller and the availability of the memory device controller may include enabling a host control mode in response to the operating state of the host controller being available and the operating state of the memory device controller being busy.

公开(公告)号：US20200348884A1

公开(公告)日：2020-11-05

申请号：US16400468

申请日：2019-05-01

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Sai Praneeth SREERAM ,  Surendra PARAVADA ,  Venu Madhav MOKKAPATI

IPC: G06F3/06

Abstract: In some aspects, the present disclosure provides a method for managing data communication rates of a memory device. The method includes receiving an input/output (I/O) operation to be performed by the memory device, detecting a temperature of the memory device, and determining whether the detected temperature satisfies a threshold condition. The threshold condition is satisfied if the detected temperature is above a first temperature threshold or below a second temperature threshold. If the threshold condition is satisfied, selecting a gear from a plurality of gears based on a ranking of the plurality of gears at the detected temperature, wherein each gear of the plurality of gears correspond to a respective one of a plurality of data rates used by the memory device for performing I/O operations, and serving, to the memory device, the I/O operation with an indication to perform the I/O operation using the selected gear.

公开(公告)号：US20240378166A1

公开(公告)日：2024-11-14

申请号：US18314676

申请日：2023-05-09

Applicant: QUALCOMM INCORPORATED

Inventor： Madhu Yashwanth BOENAPALLI ,  Kaustub Naidu PAILA RAM ,  Sravani DEVINENI ,  Sai Praneeth SREERAM ,  Vinod KUMAR KURUMA ,  Rajendra Varma PUSAPATI ,  Surendra PARAVADA

IPC: G06F13/42

Abstract: A Peripheral Component Interconnect Express (PCIe) system is configured to determine when the frequency of link speed switching needed to service incoming and upcoming client requests is too high. The system is also configured to determine a modest link speed to be used to service incoming and upcoming client requests in cases where the link speed switching that will be needed is too high and causes the incoming and upcoming client requests to be serviced at the modest link speed instead of at the link speeds associated with the predefined BWs of the clients. By doing this when the frequency of link speed switching needed is too high, the PCIe system achieves better throughput while also reducing power consumption.

公开(公告)号：US20210109674A1

公开(公告)日：2021-04-15

申请号：US16653931

申请日：2019-10-15

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA ,  Venu Madhav MOKKAPATI ,  Sai Praneeth SREERAM

IPC: G06F3/06

Abstract: In some aspects, the present disclosure provides a method for managing memory commands from a plurality of masters. The method includes receiving, at a storage driver, a plurality of memory commands from the plurality of masters and determining, by the storage driver, a number of command queues of a plurality of command queues to use to service the plurality of memory commands. In certain aspects, the method includes routing, via one or more of a plurality of lanes, the plurality of memory commands to a storage controller according to the determined number of command queues, wherein each of the plurality of lanes corresponds to one of the plurality of command queues and storing, by the storage controller, one or more of the plurality of memory commands in each of the determined number of command queues.

公开(公告)号：US20200233605A1

公开(公告)日：2020-07-23

申请号：US16255477

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Hyunsuk SHIN ,  Surendra PARAVADA ,  Sai Praneeth SREERAM ,  Venu Madhav MOKKAPATI

IPC: G06F3/06

Abstract: A method of scheduling universal flash storage (UFS) operations using a refresh handover mechanism is described. The method includes receiving, during refresh of a UFS device, a request for an input/output (I/O) operation. The method also includes handing over between a first type of refresh operation and a second type of refresh operation in response to the request for the I/O operation.

公开(公告)号：US20190304552A1

公开(公告)日：2019-10-03

申请号：US15942380

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA ,  Sai Praneeth SREERAM ,  Venu Madhav MOKKAPATI

IPC: G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G11C16/32 ,  G06F3/06

Abstract: An embodiment is directed to an apparatus that comprises a host controller and a flash memory. The host controller monitors a temperature in a first memory block of the flash memory (e.g., based on a reported temperature measurements from the flash memory), and selectively synchronizes a first refresh of the first memory block with a second refresh of a second memory block of the flash memory based in part upon the monitored temperature. For example, an immediate refresh of the first memory block may be performed if there is a pending I/O request for the first memory block, an error rate associated with the first memory block exceeds an error rate threshold and/or the monitored temperature of the first memory block exceeds a temperature threshold; otherwise, a synchronized refresh of the first and second memory blocks may be executed.

公开(公告)号：US20250103232A1

公开(公告)日：2025-03-27

申请号：US18472959

申请日：2023-09-22

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Sai Praneeth SREERAM ,  Surendra PARAVADA

IPC: G06F3/06

Abstract: A host device includes a memory configured to store a logical-to-physical address mapping table of a flash memory device. The host device also includes one or more processors coupled to the memory and configured to be coupled to the flash memory device. The one or more processors are configured to determine whether a trigger condition is satisfied. The trigger condition is associated with checking a distribution of write data that is written to the flash memory device. The one or more processors are also configured to, based on a determination that the trigger condition is satisfied, identify a die of the flash memory device that has a higher data occupancy than at least one other die of the flash memory device, and send a command to the flash memory device to move data from the identified die to one or more other dies of the flash memory device.