公开(公告)号：US20180137896A1

公开(公告)日：2018-05-17

申请号：US15782833

申请日：2017-10-12

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk SHIN ,  David TEB ,  Hung VUONG ,  Venkatakrishnan GOPALAKRISHNAN

IPC: G11C7/10 ,  G06F12/02 ,  G06F3/06 ,  G06F13/16

CPC classification number: G11C7/1003 ,  G06F3/0619 ,  G06F12/0246 ,  G06F13/102 ,  G06F13/1668 ,  G06F13/4247

Abstract: In conventional systems with a plurality of UFS devices daisy-chained to a UFS host, a UFS device driver must be able to differentiate among the links, and send either link control messages or data/management (D/M) messages to a UFS host controller. This can make force the UFS device driver to be complicated and error prone. To address this issue, a host controller can provide a uniform view of a plurality of daisy-chained devices to a device driver of a host. For example, the host controller can be such that from the perspective of the device driver, each device can appear to be a point-to-point connected device. This can allow the device driver to use a same set of link control messages to control the links. In this way, the device driver can be simplified and thus less error prone.

公开(公告)号：US20170365352A1

公开(公告)日：2017-12-21

申请号：US15615827

申请日：2017-06-06

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk SHIN ,  Robert HARDACKER ,  Hung VUONG

IPC: G11C16/34 ,  G06F12/02

CPC classification number: G11C16/3431 ,  G06F12/0246 ,  G11C16/3418

Abstract: Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, refresh rate requirements, etc. A host can control the various settings for start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, through the corresponding registers; and the Flash memory can control various values related to refresh rate requirements through corresponding registers. In this manner, a standard platform or interface is provided within the Flash memory for refresh operations thereof.

公开(公告)号：US20190034106A1

公开(公告)日：2019-01-31

申请号：US16030841

申请日：2018-07-09

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk SHIN ,  Todd Christopher REYNOLDS ,  Hung VUONG

IPC: G06F3/06 ,  G06F13/16

Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

公开(公告)号：US20180107384A1

公开(公告)日：2018-04-19

申请号：US15292675

申请日：2016-10-13

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk SHIN ,  David TEB ,  Hung VUONG

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0607 ,  G06F3/0635 ,  G06F3/0679 ,  G06F13/4022

Abstract: Systems and method are directed to a Universal Flash Storage (UFS) host capable of interfacing one or more UFS devices. The UFS host includes a plurality of mobile-physical-layers (M-PHYs) for supporting one or more lanes of traffic between the UFS host and the one or more UFS devices. A Reference M-PHY MODULE Interface (RMMI) router is coupled between a Unified Protocol link layer (Unipro) and the plurality of M-PHYs. The RMMI router is configurable in a transparent mode to pass traffic, without routing, between the UFS host and a 2-lane embedded UFS device through the two M-PHYs. The RMMI router is configurable in a routing mode, to route traffic to a first M-PHY interfacing a 1-lane embedded UFS device or to a second M-PHY interfacing a 1-lane removable UFS card. The RMMI router is configurable based on metal strap or read only memory (ROM) setting.

公开(公告)号：US20190121540A1

公开(公告)日：2019-04-25

申请号：US15789903

申请日：2017-10-20

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk SHIN ,  David TEB ,  Hung VUONG

IPC: G06F3/06 ,  G06F12/02

Abstract: In a conventional system with a UFS device connected to a UFS host implementing HPB features, a UFS driver software generates commands, e.g., read and write commands, for the UFS device to perform. The commands include both physical and logical addresses of the UFS device. Typically, the UFS driver software is software based. Therefore, there is much overhead associated with implementing the HPB. To address this issue, it is proposed to enable a hardware based host controller to perform operations related to the HPB. In this way, the performance of a system may be improved.

公开(公告)号：US20190066811A1

公开(公告)日：2019-02-28

申请号：US16175745

申请日：2018-10-30

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk SHIN ,  Robert HARDACKER ,  Hung VUONG

IPC: G11C16/34 ,  G06F12/02

CPC classification number: G11C16/3431 ,  G06F12/0246 ,  G11C16/3418

Abstract: Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, refresh rate requirements, etc. A host can control the various settings for start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, through the corresponding registers; and the Flash memory can control various values related to refresh rate requirements through corresponding registers. In this manner, a standard platform or interface is provided within the Flash memory for refresh operations thereof.

公开(公告)号：US20150067234A1

公开(公告)日：2015-03-05

申请号：US14016717

申请日：2013-09-03

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk SHIN ,  Jung Pill KIM ,  Dexter Tamio CHUN ,  Jungwon SUH

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1694

Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.

Abstract translation: 提供增强的多芯片封装（eMCP），包括统一的存储器控​​制器。 UMC被配置为管理不同类型的存储器，例如eMCP上的NAND闪存和DRAM。 联电提供存储内存管理，DRAM管理，存储内存管理的DRAM可访问性和DRAM管理的存储存储器可访问性。 UMC还有助于从DRAM到存储器的直接数据复制，反之亦然。 直接复制可以由UMC发起，而无需与主机的交互，也可以由主机发起。

公开(公告)号：US20200233605A1

公开(公告)日：2020-07-23

申请号：US16255477

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Hyunsuk SHIN ,  Surendra PARAVADA ,  Sai Praneeth SREERAM ,  Venu Madhav MOKKAPATI

IPC: G06F3/06

Abstract: A method of scheduling universal flash storage (UFS) operations using a refresh handover mechanism is described. The method includes receiving, during refresh of a UFS device, a request for an input/output (I/O) operation. The method also includes handing over between a first type of refresh operation and a second type of refresh operation in response to the request for the I/O operation.

公开(公告)号：US20180039596A1

公开(公告)日：2018-02-08

申请号：US15228975

申请日：2016-08-04

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk SHIN

IPC: G06F13/42 ,  G11C14/00

CPC classification number: G06F13/4282 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/24 ,  G11C29/48 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of serial peripheral interface (SPI) communications for a resistive memory. The method includes transmitting resistive memory commands via the SPI to operate the resistive memory according to an SPI protocol. The SPI protocol includes a command byte, an address byte, and data bytes.

公开(公告)号：US20190179540A1

公开(公告)日：2019-06-13

申请号：US15838348

申请日：2017-12-11

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA ,  Hyunsuk SHIN ,  Venu Madhav MOKKAPATI

IPC: G06F3/06

Abstract: In a conventional system with an embedded UFS and an external UFS card are connected to a UFS host, the UFS host is only able to transfer data to the embedded UFS or to the an external UFS card, but not to both at the same time. To address this issue, it is proposed to provide a host that is capable of concurrently transferring data to multiple storage devices.