公开(公告)号：US10965289B2

公开(公告)日：2021-03-30

申请号：US16267289

申请日：2019-02-04

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim ,  Mickael Malabry ,  Mukul Gupta

IPC: H03K19/0948 ,  H01L27/118 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L27/092

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US10777640B2

公开(公告)日：2020-09-15

申请号：US16781820

申请日：2020-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim

IPC: H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L29/66 ,  H01L23/528 ,  H01L27/118 ,  H01L27/02

Abstract: In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.

公开(公告)号：US20190172823A1

公开(公告)日：2019-06-06

申请号：US15831991

申请日：2017-12-05

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Sorin Adrian Dobre ,  Hyeokjin Lim ,  Venugopal Boynapalli

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092 ,  G06F17/50

Abstract: In certain aspects, a semiconductor die includes a first cell and a second cell. The first cell includes first transistors, and a first interconnect structure interconnecting the first transistors to form a first circuit. The second cell includes second transistors, and a second interconnect structure interconnecting the second transistors to form a second circuit. The first circuit and the second circuit are configured to perform a same function, and a length of the first cell in a first lateral direction is greater than a length of the second cell in the first lateral direction.

公开(公告)号：US20180123568A1

公开(公告)日：2018-05-03

申请号：US15338181

申请日：2016-10-28

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H03K3/012 ,  H03K3/356 ,  H03K19/20

CPC classification number: H03K3/012 ,  H03K3/356121 ,  H03K3/356156 ,  H03K19/0016 ,  H03K19/20

Abstract: Methods and systems for clock gating are described herein. In certain aspects, a method for clock gating includes receiving an input signal of a flip-flop and an output signal of the flip-flop, and passing a clock signal to an input of a gate in the flip-flop if the input signal and the output signal have different logic values or both the input signal and the output signal have a logic value of zero. The method also includes gating the clock signal if both the input signal and the output signal have a logic value of one.

公开(公告)号：US09831272B2

公开(公告)日：2017-11-28

申请号：US15264560

申请日：2016-09-13

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Venugopal Boynapalli ,  Satyanarayana Sahu ,  Hyeokjin Lim ,  Mukul Gupta

IPC: H01L27/118 ,  H01L29/06

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L29/0642 ,  H01L29/0649 ,  H01L2027/11829 ,  H01L2027/11866

Abstract: A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.

公开(公告)号：US09490813B2

公开(公告)日：2016-11-08

申请号：US14534967

申请日：2014-11-06

Applicant: QUALCOMM Incorporated

Inventor： Kevin Robert Bowles ,  Jose Gabriel Corona ,  Venugopal Boynapalli

IPC: H03K7/00 ,  H03L5/00 ,  H03K19/0185 ,  H03K3/356 ,  H03K17/00

CPC classification number: H03K19/018528 ,  H03K3/35613 ,  H03K17/002 ,  H03K17/005 ,  H03K19/018507

Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.

Abstract translation: 本文描述了用于电平转换复用的系统和方法。 在一个实施例中，一种用于电平转换复用的方法包括：基于一个或多个选择信号选择多个输入中的一个，并且基于所述多个输入中所选择的一个输入的逻辑状态来下拉第一和第二节点中的一个 。 该方法还包括如果第二节点被拉下来则拉起第一节点，并且如果第一节点被拉下来则提起第二节点。

公开(公告)号：US20160078965A1

公开(公告)日：2016-03-17

申请号：US14488171

申请日：2014-09-16

Applicant: Qualcomm Incorporated

Inventor： Venugopal Boynapalli ,  Kashyap Ramachandra Bellur ,  Prabaharan Balu ,  Bilal Zafar ,  Alex Dongkyu Park ,  Sei Seung Yoon

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G11C8/16 ,  G11C29/20 ,  G11C29/32 ,  G11C2029/3202

Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.

Abstract translation: 示例性可扫描寄存器文件包括多个存储器单元，并且扫描测试的移位阶段将数据位从通过多个存储器单元的扫描输入移位到扫描输出。 可以通过在每个时钟周期读取多个存储器单元中的一个以提供扫描输出并将多个存储器单元中的一个与扫描输入上的数据位一起写入来执行移位。 为了在每个时钟周期执行顺序读取和写入，可扫描寄存器可以产生一个写入时钟，在写入时钟期间，在移位阶段，与用于功能操作的时钟相反。 写时钟不产生毛刺，因此不会发生意外的写入。 可扫描寄存器文件可以集成在集成电路中的其他模块的基于扫描的测试（例如，使用自动测试模式生成）。

公开(公告)号：US09230691B1

公开(公告)日：2016-01-05

申请号：US14535097

申请日：2014-11-06

Applicant: QUALCOMM Incorporated

Inventor： Venugopal Boynapalli ,  Bilal Zafar

IPC: G11C29/00 ,  G11C11/419

CPC classification number: G11C29/70 ,  G11C11/419 ,  G11C29/765 ,  G11C29/808 ,  G11C29/886

Abstract: A cross-bar switch is provided that enables each master from a plurality of masters to read from and write to selected memories from an array of memories. A logic circuit controls the cross-bar switch so that redundancy for the memories is provided by a shared redundancy storage element.

Abstract translation: 提供了一种横杆开关，其使得来自多个主器件的每个主器件能够从存储器阵列读取和写入所选择的存储器。 逻辑电路控制交叉开关，使得存储器的冗余由共享冗余存储元件提供。

公开(公告)号：US11133803B2

公开(公告)日：2021-09-28

申请号：US15929520

申请日：2020-05-07

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim ,  Mickael Malabry ,  Mukul Gupta

IPC: H03K19/0948 ,  H01L27/118 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L27/092

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US10692808B2

公开(公告)日：2020-06-23

申请号：US15707807

申请日：2017-09-18

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad Hiremath ,  Hyeokjin Lim ,  Foua Vang ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092

Abstract: In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.