公开(公告)号：US20240371806A1

公开(公告)日：2024-11-07

申请号：US18313020

申请日：2023-05-05

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Jun CHEN ,  Yangyang SUN ,  Lily ZHAO ,  Ahmer SYED

IPC: H01L23/00 ,  H01L23/31

Abstract: Disclosed are techniques for integrated circuit device. In an aspect, an integrated circuit device includes a metallization structure that includes a top metal layer structure; a passivation layer on the metallization structure; a bump structure disposed on the first bump line structure; and a first polymer protection layer. The passivation layer may include one or more first openings. The first bump line structure may include one or more first extended portions respectively extending toward the top metal layer structure through the one or more first openings. The bump structure may be electrically coupled to the first bump line structure. The first polymer protection layer may be on the passivation layer, on a portion of the first bump line structure, and in contact with a side surface of the first bump line structure.

公开(公告)号：US20240055383A1

公开(公告)日：2024-02-15

申请号：US17819269

申请日：2022-08-11

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Hung-Yuan HSU ,  Yangyang SUN ,  Lily ZHAO

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/13 ,  H01L24/04 ,  H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/03912 ,  H01L2224/0345 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/11849 ,  H01L2224/11462 ,  H01L2224/11912

Abstract: Disclosed are techniques for selectively boosting conductive pillar bumps. In an aspect, an apparatus includes a plurality of metal pads, a first set of boosting pads attached to a first set of the plurality of metal pads, a first set of conductive pillar bumps attached to the first set of boosting pads, a second set of conductive pillar bumps attached to a second set of the plurality of metal pads, wherein heights of the first set of conductive pillar bumps are shorter than heights of the second set of conductive pillar bumps, and wherein heights of the first set of boosting pads plus the heights of the first set of conductive pillar bumps are within a tolerance threshold of the heights of the second set of conductive pillar bumps, and solder attached to the first set of conductive pillar bumps and the second set of conductive pillar bumps.

公开(公告)号：US20230082120A1

公开(公告)日：2023-03-16

申请号：US17476373

申请日：2021-09-15

Applicant: QUALCOMM Incorporated

Inventor： Yujen CHEN ,  Hung-Yuan HSU ,  Dongming HE

IPC: H01L23/00 ,  H01L23/498

Abstract: A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects comprises a first pillar interconnect. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width and a second pillar interconnect portion comprising a second width that is different than the first width.

公开(公告)号：US20230057439A1

公开(公告)日：2023-02-23

申请号：US17409334

申请日：2021-08-23

Applicant: QUALCOMM Incorporated

Inventor： Yujen CHEN ,  Hung-Yuan HSU ,  Dongming HE

IPC: H01L23/00

Abstract: A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first pillar interconnect. A planar cross section that extends through the first cavity of the first pillar interconnect may comprise an O shape. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width; and a second pillar interconnect portion comprising a second width that is different than the first width.

公开(公告)号：US20210210449A1

公开(公告)日：2021-07-08

申请号：US17027316

申请日：2020-09-21

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Hung-Yuan HSU ,  Yangyang SUN ,  Wei HU ,  Wei WANG ,  Lily ZHAO

IPC: H01L23/00

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.