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公开(公告)号:US20190244920A1
公开(公告)日:2019-08-08
申请号:US16384136
申请日:2019-04-15
发明人: Wen-Hsiung Lu , Hsuan-Ting Kuo , Tsung-Yuan Yu , Hsien-Wei Chen , Ming-Da Cheng , Chung-Shi Liu
IPC分类号: H01L23/00 , H01L21/768 , H01L23/532 , H01L23/525 , H01L23/29 , H01L21/56 , H01L23/31
CPC分类号: H01L24/11 , H01L21/566 , H01L21/76885 , H01L23/293 , H01L23/3192 , H01L23/525 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/02331 , H01L2224/0345 , H01L2224/0347 , H01L2224/036 , H01L2224/0362 , H01L2224/03828 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05186 , H01L2224/05548 , H01L2224/05569 , H01L2224/05582 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/10126 , H01L2224/1112 , H01L2224/11334 , H01L2224/1134 , H01L2224/11462 , H01L2224/1148 , H01L2224/1181 , H01L2224/11849 , H01L2224/1191 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16238 , H01L2224/81191 , H01L2224/814 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2924/04953 , H01L2924/181 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
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公开(公告)号:US20190229048A1
公开(公告)日:2019-07-25
申请号:US16371356
申请日:2019-04-01
发明人: Shuo-Mao Chen , Der-Chyang Yeh , Chiung-Han Yeh
IPC分类号: H01L23/498 , H01L21/56 , H01L23/00 , H01L23/538
CPC分类号: H01L23/49822 , H01L21/568 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/05 , H01L24/19 , H01L2224/02233 , H01L2224/02331 , H01L2224/02381 , H01L2224/03 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05026 , H01L2224/05099 , H01L2224/05124 , H01L2224/05147 , H01L2224/05552 , H01L2224/05572 , H01L2224/0558 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/06051 , H01L2224/06515 , H01L2224/12105 , H01L2224/13005 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/96 , H01L2924/00014 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19103 , H01L2924/206 , H01L2924/014 , H01L2924/00012 , H01L2224/11 , H01L2924/01047 , H01L2924/00
摘要: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
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公开(公告)号:US20190198376A1
公开(公告)日:2019-06-27
申请号:US16293201
申请日:2019-03-05
IPC分类号: H01L21/683 , H01L23/00 , H01L23/31 , H01L21/48 , H01L21/56
CPC分类号: H01L21/6835 , H01L21/4832 , H01L21/561 , H01L21/568 , H01L21/6836 , H01L21/78 , H01L23/3107 , H01L23/3114 , H01L23/36 , H01L23/49537 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2221/68304 , H01L2221/68327 , H01L2221/68377 , H01L2221/68381 , H01L2224/04105 , H01L2224/11 , H01L2224/11003 , H01L2224/11312 , H01L2224/1132 , H01L2224/11334 , H01L2224/11418 , H01L2224/1146 , H01L2224/11462 , H01L2224/116 , H01L2224/119 , H01L2224/1308 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/1319 , H01L2224/16245 , H01L2224/16258 , H01L2224/27003 , H01L2224/27312 , H01L2224/2732 , H01L2224/27334 , H01L2224/27418 , H01L2224/2746 , H01L2224/27462 , H01L2224/276 , H01L2224/279 , H01L2224/2908 , H01L2224/291 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29166 , H01L2224/2919 , H01L2224/32245 , H01L2224/32258 , H01L2224/33181 , H01L2224/45015 , H01L2224/48091 , H01L2224/4811 , H01L2224/48111 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/49109 , H01L2224/73204 , H01L2224/73265 , H01L2224/75251 , H01L2224/75252 , H01L2224/753 , H01L2224/75755 , H01L2224/75756 , H01L2224/81192 , H01L2224/8121 , H01L2224/81805 , H01L2224/81815 , H01L2224/81856 , H01L2224/83 , H01L2224/83005 , H01L2224/83191 , H01L2224/83192 , H01L2224/8321 , H01L2224/83805 , H01L2224/83815 , H01L2224/83856 , H01L2224/85005 , H01L2224/92 , H01L2224/92125 , H01L2224/92147 , H01L2224/92227 , H01L2224/94 , H01L2224/95 , H01L2224/97 , H01L2924/00014 , H01L2924/181 , H01L2924/3511 , H01L2924/0665 , H01L2924/014 , H01L2224/81 , H01L2224/27 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2924/207
摘要: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
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公开(公告)号:US20190131261A1
公开(公告)日:2019-05-02
申请号:US16233218
申请日:2018-12-27
发明人: Chen-Hua Yu , Chung-Shi Liu , Ming-Da Cheng , Mirng-Ji Lii , Meng-Tse Chen , Wei-Hung Lin
IPC分类号: H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065 , B23K35/00 , B23K35/02 , B23K35/22 , B23K35/26 , B23K35/36 , H01L25/10 , H01L21/56 , H01L25/00 , H01L25/03
CPC分类号: H01L24/05 , B23K35/001 , B23K35/0222 , B23K35/22 , B23K35/262 , B23K35/3613 , H01L21/561 , H01L23/3135 , H01L23/3178 , H01L23/498 , H01L23/49816 , H01L24/08 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/03 , H01L25/0652 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05572 , H01L2224/05611 , H01L2224/06181 , H01L2224/08113 , H01L2224/1184 , H01L2224/13005 , H01L2224/13014 , H01L2224/13022 , H01L2224/13023 , H01L2224/13026 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/1355 , H01L2224/13561 , H01L2224/1357 , H01L2224/13582 , H01L2224/136 , H01L2224/13666 , H01L2224/1412 , H01L2224/14181 , H01L2224/16104 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17051 , H01L2224/48091 , H01L2224/48227 , H01L2224/81815 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/381 , H01L2924/3841 , H01L2924/00 , H01L2224/81 , H01L2924/01047 , H01L2924/01029 , H01L2924/01083 , H01L2924/013 , H01L2924/206 , H01L2224/05552 , H01L2924/00012
摘要: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.
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公开(公告)号:US20190027459A1
公开(公告)日:2019-01-24
申请号:US16139040
申请日:2018-09-23
申请人: Ping-Jung Yang
发明人: Ping-Jung Yang
IPC分类号: H01L23/00 , H05K1/09 , H01L23/15 , H01L23/498 , H01L51/00 , H05B33/08 , H01G4/12 , H01L25/16
CPC分类号: H01L24/30 , H01G4/129 , H01L23/15 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L24/13 , H01L24/16 , H01L24/46 , H01L24/48 , H01L24/49 , H01L25/16 , H01L51/0096 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05599 , H01L2224/056 , H01L2224/05688 , H01L2224/05788 , H01L2224/13076 , H01L2224/1308 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/16237 , H01L2224/2919 , H01L2224/32151 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2924/01029 , H01L2924/12042 , H01L2924/12044 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H05B33/0896 , H05K1/09 , Y02E10/549 , Y02P70/521 , H01L2924/00014 , H01L2924/00 , H01L2924/014 , H01L2924/00012
摘要: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.
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公开(公告)号:US20180350764A1
公开(公告)日:2018-12-06
申请号:US16101871
申请日:2018-08-13
发明人: Chang-Chia Huang , Tsung-Shu Lin , Ming-Da Cheng , Wen-Hsiung Lu , Bor-Rung Su
IPC分类号: H01L23/00 , H01L21/56 , H01L23/482 , H01L23/498 , H01L23/538 , H01L23/48 , H01L21/768 , H01L21/302 , H01L21/28
CPC分类号: H01L24/16 , H01L21/28 , H01L21/302 , H01L21/565 , H01L21/76895 , H01L23/48 , H01L23/4824 , H01L23/498 , H01L23/538 , H01L24/03 , H01L24/04 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05556 , H01L2224/05567 , H01L2224/05572 , H01L2224/056 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16238 , H01L2224/81191 , H01L2224/81815 , H01L2924/00012 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要: The present disclosure relates a method of forming an integrated chip packaging device. In some embodiments, the method may be performed by forming a conductive trace on a surface of a packaging component. The conductive trace has an angled surface defining an undercut. A molding material is deposited over an entirety of the conductive trace and within the undercut. The molding material is removed from an upper surface of the conductive trace. The molding material has a sloped outermost sidewall after removing the molding material from the upper surface. A solder region is formed on the upper surface of the conductive trace.
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公开(公告)号:US20180315698A1
公开(公告)日:2018-11-01
申请号:US16029030
申请日:2018-07-06
发明人: JinGyu Kim , Taehun Kim , JiSun Hong , Byungmoon Bae , Se-Ho You
IPC分类号: H01L23/498 , H01L23/60
CPC分类号: H01L23/49838 , H01L23/293 , H01L23/49816 , H01L23/562 , H01L23/60 , H01L24/13 , H01L24/16 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16237 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/3511
摘要: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.
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公开(公告)号:US20180301436A1
公开(公告)日:2018-10-18
申请号:US16008531
申请日:2018-06-14
申请人: Invensas Corporation
发明人: Cyprian Emeka Uzoh , Rajesh Katkar
IPC分类号: H01L25/065 , H01L49/02 , B81B7/00 , H01L25/00 , H01L25/16 , H01L23/00 , H01L23/538 , H01L23/522 , H01L23/498 , H01L23/48 , H01L23/42 , H01L23/367 , H01L21/48
CPC分类号: H01L25/0657 , B81B7/0074 , H01L21/4853 , H01L23/3675 , H01L23/42 , H01L23/481 , H01L23/49811 , H01L23/522 , H01L23/5383 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/24 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/16 , H01L25/50 , H01L28/10 , H01L28/20 , H01L28/40 , H01L2224/0239 , H01L2224/0332 , H01L2224/0333 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03614 , H01L2224/0391 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/04042 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05184 , H01L2224/05547 , H01L2224/05565 , H01L2224/05568 , H01L2224/05569 , H01L2224/05611 , H01L2224/05616 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/05684 , H01L2224/1134 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11903 , H01L2224/1191 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/13184 , H01L2224/13565 , H01L2224/13616 , H01L2224/1403 , H01L2224/14131 , H01L2224/14132 , H01L2224/14134 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16265 , H01L2224/17181 , H01L2224/24147 , H01L2224/24227 , H01L2224/244 , H01L2224/32145 , H01L2224/3303 , H01L2224/33181 , H01L2224/45015 , H01L2224/45147 , H01L2224/48091 , H01L2224/48149 , H01L2224/4903 , H01L2224/73201 , H01L2224/73253 , H01L2224/73265 , H01L2224/81192 , H01L2224/81193 , H01L2224/81825 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06562 , H01L2225/06568 , H01L2924/00014 , H01L2924/01074 , H01L2924/01082 , H01L2924/01322 , H01L2924/12042 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/16251 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/3841 , H01L2924/00 , H01L2924/01029 , H01L2924/014 , H01L2924/00012 , H01L2924/01028 , H01L2224/05 , H01L2224/13 , H01L2224/81 , H01L2224/45099
摘要: Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.
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公开(公告)号:US20180268724A1
公开(公告)日:2018-09-20
申请号:US15918872
申请日:2018-03-12
发明人: Barry L. JENKINS
CPC分类号: G08G5/0069 , G05D1/0022 , G06T15/40 , G06T17/05 , G08G5/0008 , G08G5/0013 , G08G5/0039 , G08G5/0052 , G08G5/0056 , G08G5/0082 , G08G5/0086 , G08G5/025 , G08G5/045 , H01L23/3114 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03912 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05186 , H01L2224/05569 , H01L2224/05583 , H01L2224/05655 , H01L2224/05681 , H01L2224/05686 , H01L2224/11 , H01L2224/11334 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13561 , H01L2224/13611 , H01L2224/13613 , H01L2224/13616 , H01L2224/13639 , H01L2224/13647 , H01L2224/13655 , H01L2224/13681 , H01L2224/13686 , H01L2924/01046 , H01L2924/04941 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2924/04953 , H01L2924/014 , H01L2924/01079 , H01L2924/01028 , H01L2924/01026 , H01L2924/01027 , H01L2924/01047
摘要: A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route.
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公开(公告)号:US20180261551A1
公开(公告)日:2018-09-13
申请号:US15456972
申请日:2017-03-13
发明人: Goo Lee , KyungMoon Kim , SooSan Park , KeoChang Lee
IPC分类号: H01L23/552 , H01L21/56 , H01L21/3105 , H01L23/31 , H01L25/16 , H01L25/065 , H01L25/00 , H01L23/053 , H01L23/538 , H01L23/00
CPC分类号: H01L23/552 , H01L21/56 , H01L23/16 , H01L23/3128 , H01L23/49816 , H01L23/5383 , H01L23/5384 , H01L24/17 , H01L24/32 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/11334 , H01L2224/1146 , H01L2224/13023 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16235 , H01L2224/16238 , H01L2224/2919 , H01L2224/48091 , H01L2224/48179 , H01L2224/73265 , H01L2224/81815 , H01L2924/00014 , H01L2924/1203 , H01L2924/1304 , H01L2924/1421 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/014 , H01L2224/45099
摘要: A semiconductor device has a partition fence disposed between a first attach area and a second attach area on a substrate. A first electrical component is disposed over the first attach area. A second electrical component is disposed over the second attach area. The partition fence extends above and along a length of the first electrical component and second electrical component. An encapsulant is deposited over the substrate, first electrical component, second electrical component, and partition fence. A portion of the encapsulant is removed to expose a surface of the partition fence and planarizing the encapsulant. A shielding layer is formed over the encapsulant and in contact with the surface of the partition fence. The combination of the partition fence and shielding layer compartmentalize the first electrical component and second electrical component for physical and electrical isolation to reduce the influence of EMI, RFI, and other inter-device interference.
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