公开(公告)号：US20190206984A1

公开(公告)日：2019-07-04

申请号：US15860005

申请日：2018-01-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Jun CHEN ,  Yangyang SUN ,  Stanley Seungchul SONG ,  Giridhar NALLAPATI

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a substrate, a first group of metal layers including a plurality of first fingers over the substrate, wherein the first fingers are formed without a via. The integrated circuit may further include a second group of metal layers including a plurality of second fingers over the first group of metal layers, wherein the second fingers are formed with vias, and wherein the first and the second group of metal layers are formed by a processing technology node of 7 nm or below.

公开(公告)号：US20240355781A1

公开(公告)日：2024-10-24

申请号：US18628469

申请日：2024-04-05

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Xuefeng ZHANG ,  Jun CHEN ,  Lily ZHAO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2924/1306 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A device includes an integrated device. The integrated device includes a die that is at least partially encapsulated. The die includes a conductive pad. The device also includes a first passivation layer coupled to a first surface of the die. The device includes an offset interconnect extending along a surface of the first passivation layer and including a portion that extends through an opening in the first passivation layer to contact the conductive pad. The device includes a bump including a portion that extends through an opening in a second passivation layer to contact the offset interconnect. The bump is offset, in a direction along a surface of the second passive layer, from the conductive pad.

公开(公告)号：US20210125862A1

公开(公告)日：2021-04-29

申请号：US16664677

申请日：2019-10-25

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Junjing BAO ,  Jun CHEN ,  Giridhar NALLAPATI

IPC: H01L21/768

Abstract: Aspects of the disclosure are directed to super via integration. In accordance with one aspect, an apparatus with super via integration in an integrated circuit including a first metal layer; a second metal layer, wherein the second metal layer is adjacent to the first metal layer; a third metal layer, wherein the third metal layer is adjacent to the second metal layer and is non-adjacent to the first metal layer; and a super via interconnecting the first metal layer and the third metal layer through a dielectric material, wherein the super via is filled with a selective metal.

公开(公告)号：US20240371806A1

公开(公告)日：2024-11-07

申请号：US18313020

申请日：2023-05-05

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Jun CHEN ,  Yangyang SUN ,  Lily ZHAO ,  Ahmer SYED

IPC: H01L23/00 ,  H01L23/31

Abstract: Disclosed are techniques for integrated circuit device. In an aspect, an integrated circuit device includes a metallization structure that includes a top metal layer structure; a passivation layer on the metallization structure; a bump structure disposed on the first bump line structure; and a first polymer protection layer. The passivation layer may include one or more first openings. The first bump line structure may include one or more first extended portions respectively extending toward the top metal layer structure through the one or more first openings. The bump structure may be electrically coupled to the first bump line structure. The first polymer protection layer may be on the passivation layer, on a portion of the first bump line structure, and in contact with a side surface of the first bump line structure.

公开(公告)号：US20170077090A1

公开(公告)日：2017-03-16

申请号：US14852954

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  John Jianhong ZHU ,  Jun CHEN ,  Da YANG ,  Choh Fei YEAP

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/0696 ,  H01L29/66545

Abstract: A multi-cell transistor includes gate body elements, gate tip elements extending from the gate body elements, and gate extensions extending from the gate tip elements. A patterned metal layer is provided between adjacent gate elements and at least portions of adjacent gate tip elements. Spacers are provided on the sides of each gate body element and each gate tip element to prevent the patterned metal layer from creating a short circuit between adjacent gate tip elements.

Abstract translation: 多单元晶体管包括门体元件，从栅极体元件延伸的栅极尖端元件以及从栅极尖端元件延伸的栅极延伸。 在相邻的栅极元件和相邻栅极尖端元件的至少一部分之间提供图案化的金属层。 隔板设置在每个门体元件和每个门尖元件的侧面上，以防止图案化的金属层在相邻的门尖元件之间产生短路。