公开(公告)号：US11764489B2

公开(公告)日：2023-09-19

申请号：US17568596

申请日：2022-01-04

Applicant: QUALCOMM Incorporated

Inventor： Milind Shah ,  Chin-Kwan Kim ,  Jaehyun Yeon ,  Rajneesh Kumar ,  Suhyung Hwang

IPC: H01Q23/00 ,  H01Q1/24 ,  H01Q21/06 ,  H01Q21/30 ,  H01Q9/04

CPC classification number: H01Q23/00 ,  H01Q1/241 ,  H01Q1/243 ,  H01Q9/0414 ,  H01Q21/065 ,  H01Q21/068 ,  H01Q21/30

Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate. The active circuit includes a power management (PM) chip and a radio frequency (RF) chip coupled to a second package substrate coupled to the first package substrate.

公开(公告)号：US11735804B2

公开(公告)日：2023-08-22

申请号：US16871822

申请日：2020-05-11

Applicant: QUALCOMM Incorporated

Inventor： Chaoqi Zhang ,  Suhyung Hwang ,  Jaehyun Yeon ,  Taesik Yang ,  Jeongil Jay Kim ,  Darryl Sheldon Jessie ,  Mohammad Ali Tassoudji

IPC: H01Q1/38 ,  H01Q1/12 ,  H05K1/02 ,  H05K3/00 ,  H05K3/46

CPC classification number: H01Q1/12 ,  H05K1/0243 ,  H05K3/0047 ,  H05K3/4644 ,  H05K2201/10098

Abstract: A multi-core broadband printed circuit board (PCB) antenna and methods for fabricating such an antenna are provided. One example antenna implemented with a multi-core PCB generally includes a first core structure, a second core structure disposed above the first core structure, and one or more metal layers disposed above the second core structure or below the first core structure. The first core structure includes a first core layer, a first metal layer disposed below the first core layer, and a second metal layer disposed above the first core layer. The second core structure includes a second core layer, a third metal layer disposed below the second core layer, and a fourth metal layer disposed above the second core layer. The first core layer and the second core layer may have different thicknesses.

公开(公告)号：US11637057B2

公开(公告)日：2023-04-25

申请号：US16724247

申请日：2019-12-21

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Chin-Kwan Kim ,  Aniket Patil ,  Jaehyun Yeon

IPC: H01L23/498 ,  H01L21/48

Abstract: Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.

公开(公告)号：US20230014567A1

公开(公告)日：2023-01-19

申请号：US17375289

申请日：2021-07-14

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun Yeon ,  Kun Fang ,  Suhyung Hwang ,  Hyunchul Cho

IPC: H01Q1/22 ,  H01Q13/10 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H01L21/48

Abstract: Package substrates employing integrated slot-shaped antenna(s), and related integrated circuit (IC) packages and fabrication methods. The package substrate can be provided in a radio-frequency (RF) IC (RFIC) package. The package substrate includes one or more slot-shaped antennas each formed from a slot disposed in the metallization substrate that can be coupled to the RFIC die for receiving and radiating RF signals. The slot-shaped antenna includes a conductive slot disposed in at least one metallization layer in the package substrate. A metal interconnect in a metallization layer in the package substrate is coupled to the conductive slot to provide an antenna feed line for the slot-shaped antenna. In this manner, the slot-shaped antenna being integrated into the metallization substrate of the IC package can reduce the area in the IC package needed to provide an antenna and/or provide other directions of antenna radiation patterns for enhanced directional RF performance.

公开(公告)号：US11551939B2

公开(公告)日：2023-01-10

申请号：US17010693

申请日：2020-09-02

Applicant: QUALCOMM Incorporated

Inventor： Kun Fang ,  Jaehyun Yeon ,  Suhyung Hwang ,  Hong Bok We

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.

公开(公告)号：US11239573B2

公开(公告)日：2022-02-01

申请号：US16886086

申请日：2020-05-28

Applicant: QUALCOMM Incorporated

Inventor： Milind Shah ,  Chin-Kwan Kim ,  Jaehyun Yeon ,  Rajneesh Kumar ,  Suhyung Hwang

IPC: H01Q23/00 ,  H01Q21/06 ,  H01Q21/30 ,  H01Q1/24 ,  H01Q9/04

Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate.

公开(公告)号：US12126071B2

公开(公告)日：2024-10-22

申请号：US17653061

申请日：2022-03-01

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun Yeon ,  Kun Fang ,  Suhyung Hwang ,  Hyunchul Cho

IPC: H01Q1/22 ,  H01Q9/04 ,  H01Q21/08 ,  H01Q23/00

CPC classification number: H01Q1/2283 ,  H01Q9/0414 ,  H01Q21/08 ,  H01Q23/00

Abstract: Multi-directional antenna modules employing a surface-mount antenna(s) to support antenna pattern mufti-directionality, and related fabrication methods. The antenna module includes a radio-frequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and multiple antennas in the package substrate. To provide multi-directionality in antenna radiation patterns, a first antenna is provided that is coupled to the package substrate and oriented in a first plane, and a second antenna is provided that coupled to the package substrate and oriented in a second plane orthogonal to the first plane. In an example, the second antenna is packaged in an antenna package that includes external metal pads that when surface mounted to the package substrate, cause the second antenna to oriented in the second plane.

公开(公告)号：US12125742B2

公开(公告)日：2024-10-22

申请号：US17479691

申请日：2021-09-20

Applicant: QUALCOMM Incorporated

Inventor： Hyunchul Cho ,  Kun Fang ,  Jaehyun Yeon ,  Suhyung Hwang

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/76816 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/04105 ,  H01L2224/16227

Abstract: A package that includes a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes at least one dielectric layer, a first plurality of high-density interconnects located in the at least one dielectric layer and through a first surface of the at least one dielectric layer; a second plurality of high-density interconnects located in the at least one dielectric.

公开(公告)号：US11869833B2

公开(公告)日：2024-01-09

申请号：US17476383

申请日：2021-09-15

Applicant: QUALCOMM Incorporated

Inventor： Kun Fang ,  Jaehyun Yeon ,  Suhyung Hwang ,  Hyunchul Cho

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49838 ,  H01L23/3128 ,  H01L24/16 ,  H01L2224/16227

Abstract: A package that includes a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a first via interconnect and a first trace interconnect, wherein the first via interconnect is directly coupled to the first trace interconnect. The first via interconnect is coupled to the first trace interconnect without an intervening pad interconnect between the first via interconnect and the first trace interconnect.

公开(公告)号：US11823983B2

公开(公告)日：2023-11-21

申请号：US17210314

申请日：2021-03-23

Applicant: QUALCOMM Incorporated

Inventor： Kun Fang ,  Jaehyun Yeon ,  Suhyung Hwang ,  Hong Bok We

IPC: H01L23/482 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/482 ,  H01L23/528 ,  H01L23/5226

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate comprises at least one dielectric layer; a plurality of interconnects comprising plurality of pad-on-pad interconnects, wherein the plurality of pad-on-pad interconnects is embedded through a first surface of the substrate. The plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect comprising a first pad and a second pad coupled to the first pad. The package further comprising a solder resist layer located over the first surface of the substrate. The solder resist layer comprises a first solder resist layer portion comprising a first thickness; and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The second solder resist layer portion is located between the at least one dielectric layer and the integrated device.