公开(公告)号：US20180260357A1

公开(公告)日：2018-09-13

申请号：US15453678

申请日：2017-03-08

Applicant: QUALCOMM Incorporated

Inventor： Yossi Amon ,  Lior Amarilio ,  Ofer Rosenberg

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/404 ,  G06F2213/0016

Abstract: Systems, methods, and apparatus are described that enable an I3C master device to support I2C clock stretch used by I2C devices connected to an I3C bus. A method performed at a master device includes enabling a line driver to drive a clock wire of the serial bus in accordance with a clock signal and when the master device is configured for a first mode of operation, enabling the line driver to drive the clock wire to a first voltage level when the clock signal is in a first signaling state and when the master device is configured for a second mode of operation, and disabling the line driver when the clock signal is in a second signaling state in the second mode of operation. A resistor pulls the clock wire to a second voltage level when the clock signal is in the second signaling state.

公开(公告)号：US20180120921A1

公开(公告)日：2018-05-03

申请号：US15726566

申请日：2017-10-06

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil ,  James Lionel Panian ,  Ofer Rosenberg ,  Richard Dominic Wietfeldt

IPC: G06F1/32 ,  G06F13/40 ,  H04L12/931 ,  H01L23/29

CPC classification number: G06F1/3253 ,  G06F13/4072 ,  G06F13/4273 ,  G06F13/4291 ,  H01L23/291 ,  H04L49/40 ,  Y02D10/151

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.