公开(公告)号：US12204469B2

公开(公告)日：2025-01-21

申请号：US18586867

申请日：2024-02-26

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Brent Haukness

IPC: G06F13/16 ,  G06F5/14

Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

公开(公告)号：US11947471B2

公开(公告)日：2024-04-02

申请号：US17852135

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Brent Haukness

IPC: G06F13/16 ,  G06F5/14

CPC classification number: G06F13/1626 ,  G06F5/14

Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

公开(公告)号：US20230153251A1

公开(公告)日：2023-05-18

申请号：US17992443

申请日：2022-11-22

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Trung A. Diep

IPC: G06F12/1045 ,  G06F12/0802 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1054

Abstract: The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to perform a memory access, wherein the request includes a virtual address. In response to the request, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

公开(公告)号：US11487676B2

公开(公告)日：2022-11-01

申请号：US16953230

申请日：2020-11-19

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  James Tringali

IPC: G06F12/1036 ,  G06F12/02

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

公开(公告)号：US11347665B2

公开(公告)日：2022-05-31

申请号：US16914221

申请日：2020-06-26

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A Ware

IPC: G06F13/40 ,  G06F13/16 ,  H04L47/50 ,  G06F9/48 ,  G11C11/4076 ,  G11C11/4094

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

公开(公告)号：US20210232507A1

公开(公告)日：2021-07-29

申请号：US17107831

申请日：2020-11-30

Applicant: Rambus Inc.

Inventor： Trung Diep ,  Hongzhong Zheng

IPC: G06F12/1009 ,  G06F12/0864 ,  G06F12/0811 ,  G11C7/10

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

公开(公告)号：US10891241B2

公开(公告)日：2021-01-12

申请号：US16149553

申请日：2018-10-02

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Trung A. Diep

IPC: G06F12/00 ,  G06F12/1045 ,  G06F12/0802 ,  G06F12/1009

Abstract: The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to perform a memory access, wherein the request includes a virtual address. In response to the request, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

公开(公告)号：US10853265B2

公开(公告)日：2020-12-01

申请号：US16134758

申请日：2018-09-18

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  James Tringali

IPC: G06F12/1036 ,  G06F12/02

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

公开(公告)号：US09158672B1

公开(公告)日：2015-10-13

申请号：US13644550

申请日：2012-10-04

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Brent Steven Haukness

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/023 ,  G06F12/0238 ,  G06F2212/1024 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: A memory storage scheme specially adapted for wear leveling (or other reorganization of logical memory space). Memory space includes a logical memory space of M addressable blocks of data, stored as rows or pages, and N substitute rows or pages. Data is periodically shuffled by copying data from one of the M addressable blocks to a substitute row, with the donating row then becoming part of substitute memory space, available for ensuing wear leveling operations, using a stride address. The disclosed techniques enable equation-based address translation, obviating need for an address translation table. An embodiment performs address translation entirely in hardware, for example, integrated with a memory device to perform wear leveling or data scrambling, in a manner entirely transparent to a memory controller. In addition, the stride address can represent an offset greater than one (e.g., greater than one row) and can be dynamically varied.

Abstract translation: 专门用于磨损均衡（或逻辑内存空间的其他重组）的存储器存储方案。 存储器空间包括存储为行或页面的M个可寻址数据块的逻辑存储空间，以及N个替代行或页面。 通过将数据从M个可寻址块中的一个复制到替代行来周期性地进行数据洗牌，然后捐赠行成为替代存储器空间的一部分，可用于随后进行的磨损均衡操作，使用跨步地址。 所公开的技术使得基于方程式的地址转换不需要地址转换表。 一个实施例，以对于存储器控制器完全透明的方式，完全在硬件上执行地址转换，例如与存储器件集成以执行损耗均衡或数据加扰。 此外，步幅地址可以表示大于1的偏移（例如，大于一行），并且可以动态地变化。

公开(公告)号：US09104646B2

公开(公告)日：2015-08-11

申请号：US14098322

申请日：2013-12-05

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Brent Haukness ,  Mehmet Günhan Ertosun ,  Ian P. Shaeffer

IPC: G11C11/00 ,  G06F11/20

CPC classification number: G06F11/2053 ,  G11C13/0002 ,  G11C13/0033 ,  G11C16/3431 ,  G11C29/50008 ,  G11C29/52 ,  G11C2029/0409

Abstract: Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether the disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row to reduce the accumulated disturbances.

Abstract translation: 诸如存储器控制器和存储器件的存储器系统的组件，其在累积的存储器读出干扰之前检测累积的存储器读取干扰并且在达到导致错误的电平之前校正这种干扰。 存储器件包括存储器阵列和干扰控制电路。 存储器阵列包括多个存储器行。 每个存储器行与具有对应于存储器行中的累积干扰的状态的干扰警告电路相关联。 干扰控制电路响应于由行访问命令指定的多个存储行的存储器行的激活，基于与存储器相关联的干扰警告电路的状态来确定存储器行中是否存在干扰条件 行。 如果存在干扰条件，则扰动控制电路使得对存储器行进行恢复操作以减少累积的干扰。