公开(公告)号：US12250834B2

公开(公告)日：2025-03-11

申请号：US17737231

申请日：2022-05-05

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L21/765 ,  H10D30/01 ,  H10D30/65 ,  H10D62/17 ,  H10D64/00 ,  H10D84/00

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

公开(公告)号：US12107160B2

公开(公告)日：2024-10-01

申请号：US17726515

申请日：2022-04-21

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng ,  Chien-Wei Chiu

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76202 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66681

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

公开(公告)号：US20230253494A1

公开(公告)日：2023-08-10

申请号：US17847053

申请日：2022-06-22

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Yu-Ting Yeh ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/66681

Abstract: A high voltage device includes: a semiconductor layer, a well, a drift oxide region, a body region, a gate, a source, a drain, and a field plate. The well has a first conductivity type, and is formed in a semiconductor layer. The drift oxide region is formed on the semiconductor layer. The body region has a second conductivity type, and is formed in the semiconductor layer, wherein the body region and a drift region are connected in a channel direction. The gate is formed on the semiconductor layer. The source and the drain have the first conductivity type, and are formed in the semiconductor layer, wherein the source and the drain are in the body region and the well, respectively. The field plate is formed on and connected with the drift oxide region, wherein the field plate is electrically conductive and has a temperature coefficient (TC) not higher than 4 ohm/° C.

公开(公告)号：US20230046174A1

公开(公告)日：2023-02-16

申请号：US17737231

申请日：2022-05-05

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/10 ,  H01L21/765 ,  H01L29/66

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

公开(公告)号：US20220376110A1

公开(公告)日：2022-11-24

申请号：US17726515

申请日：2022-04-21

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng ,  Chien-Wei Chiu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L29/66

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

公开(公告)号：US20190115468A1

公开(公告)日：2019-04-18

申请号：US16104921

申请日：2018-08-19

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen ,  Yu-Ting Yeh

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/266

Abstract: A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.

公开(公告)号：US20180350903A1

公开(公告)日：2018-12-06

申请号：US15662277

申请日：2017-07-27

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/66681 ,  H01L29/7816

Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.