公开(公告)号：US06867113B1

公开(公告)日：2005-03-15

申请号：US09191743

申请日：1998-11-13

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/20 ,  H01L21/36

CPC classification number: H01L21/28273 ,  H01L21/28061 ,  H01L21/28525

Abstract: An in-situ deposition and doping method for polycrystalline silicon layers of semiconductor devices. A first intermediate layer of in-situ doped polycrystalline silicon is grown, and a second additional layer of polycrystalline silicon is grown with a lower doping level than that of the first intermediate layer of polycrystalline silicon. In one preferred method, the second doping level is substantially lower than the first doping level. Additionally, a semiconductor memory device of the type having a gate stack is provided. The memory device includes at least one gate layer of polycrystalline silicon, and the gate layer of polycrystalline silicon is formed from a first intermediate layer of polycrystalline silicon with a first doping level, and an overlaying second additional layer of polycrystalline silicon with a second doping level that is lower than the first doping level. In a preferred embodiment, the second doping level is substantially lower than the first doping level.

Abstract translation: 一种用于半导体器件的多晶硅层的原位沉积和掺杂方法。 生长原位掺杂多晶硅的第一中间层，并且以比多晶硅的第一中间层低的掺杂水平生长第二附加多晶硅层。 在一个优选的方法中，第二掺杂水平基本上低于第一掺杂水平。 此外，提供了具有栅极堆叠的类型的半导体存储器件。 存储器件包括多晶硅的至少一个栅极层，并且多晶硅的栅极层由具有第一掺杂水平的多晶硅的第一中间层和具有第二掺杂水平的叠加的第二附加多晶硅层形成 低于第一掺杂水平。 在优选实施例中，第二掺杂水平基本上低于第一掺杂水平。

公开(公告)号：US06627931B1

公开(公告)日：2003-09-30

申请号：US09610311

申请日：2000-07-05

Applicant: Giulio Casagrande ,  Raffaele Zambrano

Inventor： Giulio Casagrande ,  Raffaele Zambrano

IPC: H01L2976

CPC classification number: H01L27/11502 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/11507

Abstract: Presented is a memory cell integrated in a semiconductor substrate that includes a MOS device connected in series to a capacitive element. The MOS device has first and second conduction terminals, and the capacitive element has a lower electrode covered with a layer of a dielectric material and capacitively coupled to an upper electrode. The MOS device is overlaid by at least one metallization layer that is covered with at least one top insulating layer. The capacitive element is formed on the top insulating layer. The cell is unique in that the metallization layer extends only between the MOS device and the capacitive element.

Abstract translation: 提出了集成在半导体衬底中的存储单元，其包括与电容元件串联连接的MOS器件。 MOS器件具有第一和第二导电端子，并且电容元件具有被电介质材料层覆盖并且电容耦合到上电极的下电极。 MOS器件由被至少一个顶部绝缘层覆盖的至少一个金属化层覆盖。 电容元件形成在顶部绝缘层上。 该电池是唯一的，因为金属化层仅在MOS器件和电容元件之间延伸。

公开(公告)号：US06541808B2

公开(公告)日：2003-04-01

申请号：US10033508

申请日：2001-12-28

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L2348

CPC classification number: H01L27/11502 ,  H01L21/76801 ,  H01L21/76837 ,  H01L21/76877 ,  H01L27/0629 ,  H01L27/1085 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.

公开(公告)号：US06300654B1

公开(公告)日：2001-10-09

申请号：US09365187

申请日：1999-08-02

Applicant: Chiara Corvasce ,  Raffaele Zambrano

Inventor： Chiara Corvasce ,  Raffaele Zambrano

IPC: H01L2978

CPC classification number: H01L27/11502 ,  H01L27/10811 ,  H01L27/10888 ,  H01L27/115 ,  H01L27/11507

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material. In this way, the manufacturing process is not critical and the size of the cells is minimal.

Abstract translation: 层叠型电池单元包括形成在半导体材料的衬底的有源区和形成在有源区上方的电容器的MOS晶体管; 每个MOS晶体管具有第一和第二导电区域和控制电极，并且每个电容器具有由电介质区域材料（例如铁电体）隔开的第一和第二板。 每个MOS晶体管的第一导电区域连接到相应电容器的第一板，每个MOS晶体管的第二导电区域连接到相应的位线，每个MOS晶体管的控制电极连接到相应的字线， 每个电容器的第二板连接到相应的板线。 平板线垂直于位线延伸并平行于字线。 与位线平行方向相邻的至少两个单元共享相同的电介质区域材料。 以这种方式，制造过程不是关键的，并且电池的尺寸是最小的。

公开(公告)号：US06294798B1

公开(公告)日：2001-09-25

申请号：US09415992

申请日：1999-10-12

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L2904

CPC classification number: H01L27/11502 ,  H01L27/1085

Abstract: A circuit structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element that has a bottom and a top electrode. The MOS device has conduction terminals formed in the semiconductor layer, as well as a control terminal covered with an overlying insulating layer of unreflowed oxide. The capacitor element is formed on the unreflowed oxide layer.

公开(公告)号：US5895249A

公开(公告)日：1999-04-20

申请号：US604110

申请日：1996-02-20

Applicant: Raffaele Zambrano ,  Salvatore Leonardi ,  Giovanna Cacciola

Inventor： Raffaele Zambrano ,  Salvatore Leonardi ,  Giovanna Cacciola

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L29/66295 ,  H01L29/0615 ,  H01L29/1004

Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first, lightly doped ring of the first conductivity type obtained in a first, lightly doped epitaxial layer of a second conductivity type and surrounding said diffused region, and a second, lightly doped ring of the first conductivity type, comprising at least one portion superimposed on and merged with said first ring, obtained in a second, lightly doped epitaxial layer of the second conductivity type grown over the first epitaxial layer.

Abstract translation: 描述了一种用于高电压半导体器件的集成边缘结构，其包括由从半导体器件顶表面延伸的第一导电类型的扩散区域表示的PN结。 该边缘结构包括第一导电类型的第一轻掺杂环，其在第二导电类型的第一轻掺杂外延层中并且包围所述扩散区，以及第二导电类型的第二轻掺杂环，包括 在第一外延层上生长的第二导电类型的第二轻掺杂外延层中获得的至少一个部分叠加在所述第一环上并与之合并。

公开(公告)号：US5602416A

公开(公告)日：1997-02-11

申请号：US443053

申请日：1995-05-17

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L27/088 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/78 ,  H01L29/00 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L21/823878 ,  H01L27/0922

Abstract: A PIC structure comprises a lightly doped semiconductor layer of a first conductivity type, superimposed over a heavily doped semiconductor substrate of the first conductivity type, wherein a power stage and a driving and control circuitry including first conductivity type-channel MOSFETs and second conductivity type-channel MOSFETs are integrated; the first conductivity type-channel and the second conductivity type-channel MOSFETs are provided inside second conductivity type and first conductivity type well regions, respectively, which are included in at least one isolated lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer of the first conductivity type by means of a respective isolation region of a second conductivity type.

Abstract translation: PIC结构包括叠加在第一导电类型的重掺杂半导体衬底上的第一导电类型的轻掺杂半导体层，其中功率级和驱动和控制电路包括第一导电类型沟道MOSFET和第二导电类型 - 沟道MOSFET集成; 第一导电类型沟道和第二导电类型沟道MOSFET分别设置在第二导电类型和第一导电类型阱区内，所述第一导电类型和第一导电类型阱区被包括在完全包围和隔离的第一导电类型的至少一个隔离的轻掺杂区域中 所述第一导电类型的轻掺杂层通过第二导电类型的相应隔离区域。

公开(公告)号：US5565701A

公开(公告)日：1996-10-15

申请号：US908664

申请日：1992-07-02

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L27/06 ,  H01L21/331 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L29/00

CPC classification number: H01L27/0821 ,  Y10S148/096

Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.

Abstract translation: 包含电源和小信号NPN双极器件的集成电路。 小信号装置使用横向电流，并被N型阱区完全包围（横向和垂直）。 N型井区本身被P型隔离区完全包围（横向和垂直）。 这种双重隔离提供了改进的防止寄生器件接通的保护，这可能导致传统器件结构中的泄漏问题。 可选地，使用自对准工艺步骤在小信号器件中提供渐变基极掺杂分布。

公开(公告)号：US5475273A

公开(公告)日：1995-12-12

申请号：US987768

申请日：1992-12-07

Applicant: Mario Paparo ,  Raffaele Zambrano

Inventor： Mario Paparo ,  Raffaele Zambrano

IPC: H01L29/78 ,  H01L21/76 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H03K3/01

CPC classification number: H01L27/0248

Abstract: A smart power integrated circuit with dynamic isolation. A P-type isolation region surrounds the small signal devices (npn bipolar transistors and possibly other devices). This isolation region is held at ground in normal operation; but one or more pilot circuits continually monitor the collector voltages of the small-signal and power npn transistors, and instantly reconnect this isolation region, in real time, to the lowest collector voltage, whenever any of the collector voltages go below ground. Preferably a large capacitor provides a dedicated supply to the pilot circuit, so that the reconnection operation can proceed even when a power supply glitch occurs.

Abstract translation: 具有动态隔离功能的智能电源集成电路。 P型隔离区包围小信号器件（npn双极型晶体管和可能的其他器件）。 这种隔离区在正常运行中保持在地面; 但是一个或多个导频电路连续监视小信号和功率npn晶体管的集电极电压，并且每当集电极电压低于地电压时，立即将该隔离区域实时地重新连接到最低的集电极电压。 优选地，大电容器为导频电路提供专用电源，使得即使当发生电源毛刺时，重新连接操作也可以进行。

公开(公告)号：US5464993A

公开(公告)日：1995-11-07

申请号：US124245

申请日：1993-09-20

Applicant: Raffaele Zambrano ,  Sergio Palara

Inventor： Raffaele Zambrano ,  Sergio Palara

IPC: H01L27/06 ,  H01L29/10

CPC classification number: H01L27/0617

Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1,M2) together with vertically-conducting bipolar junction transistors transistors (T1,T2). These IGBT transistors are laterally conducting, having drain terminals (9,19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1,T2) of the bipolar type.

Abstract translation: 一种适合功率应用的单片集成的晶体管桥式电路，包括至少一对IGBT晶体管（M1，M2）以及垂直导电的双极结型晶体管晶体管（T1，T2）。 这些IGBT晶体管是侧向导通的，具有形成在集成电路（1）的表面上的漏极端子（9,19），并且通过这些端子连接到双极型的另一对晶体管（T1，T2）。