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公开(公告)号：US08027825B2
公开(公告)日：2011-09-27
申请号：US12130675
申请日：2008-05-30
CPC分类号： G01R31/31704 , G01R31/318357 , G06F17/5022
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括用于执行系统的通用操作的通用计算资源。 专用计算资源与通用计算资源相连。 专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件。
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公开(公告)号：US08006155B2
公开(公告)日：2011-08-23
申请号：US11621361
申请日：2007-01-09
IPC分类号： G01R31/28
CPC分类号： G06F17/5022 , G01R31/31704 , G01R31/318357 , G06F11/261
摘要： A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for: storing test patterns, a description of integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.
摘要翻译： 提供通用计算资源用于执行系统的通用操作。 专用计算资源与通用计算资源相连。 专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件。
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公开(公告)号：US07386775B2
公开(公告)日：2008-06-10
申请号：US11206846
申请日：2005-08-18
CPC分类号： G01R31/318583
摘要： Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.
摘要翻译： 公开了用于待测仿真设备（'DUT'）的扫描验证的方法，装置和产品，DUT具有扫描链，扫描输入和扫描输出，其包括验证从DUT的扫描输入的正确数据输入到 扫描链的开始，验证扫描输入和扫描输出之间的扫描链中的扫描数据的正确传播，验证从扫描链的末端输出到扫描输出的正确数据，并对具有未确定状态的扫描链进行泄漏测试 用于扫描链中的扫描单元。
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14.发明授权公开(公告)号：US07350124B2
公开(公告)日：2008-03-25
申请号：US11252512
申请日：2005-10-18
IPC分类号： G06F11/00
CPC分类号： G06F17/5022 , G01R31/318357
摘要： The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.
摘要翻译： 本发明提供一种用于对TTP-LBIST应用外部时钟和数据模式的方法，装置和计算机程序产品。 在仿真器中设置了被测逻辑的仿真模型。 接下来，用户设置外部LBIST块，其包括预先验证的内部时钟和数据模式逻辑，并将该块连接到仿真模型中的逻辑。 内部时钟和数据模式逻辑提供了用于LBIST的OPCG模式的输入模式。 该内部时钟和数据模式逻辑已经通过设计工作进行了验证。 因此，内部模式发生器成为模拟模型中的外部模式发生器。 外部LBIST块应用外部时钟和数据模式，随后用户接收并处理这些输出模式以确定逻辑是否正常工作。
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公开(公告)号：US20070061644A1
公开(公告)日：2007-03-15
申请号：US11206846
申请日：2005-08-18
IPC分类号： G01R31/28
CPC分类号： G01R31/318583
摘要： Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.
摘要翻译： 公开了用于待测仿真设备（'DUT'）的扫描验证的方法，装置和产品，DUT具有扫描链，扫描输入和扫描输出，其包括验证从DUT的扫描输入的正确数据输入到 扫描链的开始，验证扫描输入和扫描输出之间的扫描链中的扫描数据的正确传播，验证从扫描链的末端输出到扫描输出的正确数据，并对具有未确定状态的扫描链进行泄漏测试 用于扫描链中的扫描单元。
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公开(公告)号：US20060190874A1
公开(公告)日：2006-08-24
申请号：US11065601
申请日：2005-02-24
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G06F17/5022 , G06F17/504
摘要： A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level description of the design. A testbench is generated from the high-level description of the design and the constrained drivers and a formal equivalence is evaluated on the testbench to perform verification.
摘要翻译： 公开了一种用于执行验证的方法，系统和计算机程序产品。 创建对设计的高级描述，并从设计的高级描述合成约束的驱动程序。 测试台是从设计的高级描述和受限制的驱动程序生成的，并且在测试台上进行正式的等效性来执行验证。
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17.发明授权Method for switching between two redundant oscillator signals within an alignment element 有权用于在对准元件内切换两个冗余振荡器信号的方法公开(公告)号：US08055931B2
公开(公告)日：2011-11-08
申请号：US12246123
申请日：2008-10-06
申请人： Ralf Ludewig , Thuyen Le , Tilman Gloekler , Willm Hinrichs
发明人： Ralf Ludewig , Thuyen Le , Tilman Gloekler , Willm Hinrichs
IPC分类号： G06F1/04
CPC分类号： G06F1/12
摘要： A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. The method comprises introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected. The method further comprises sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed.
摘要翻译： 提供了一种用于在对准元件内的两个振荡器信号之间切换的方法。 根据该方法，选择两个振荡器信号之一作为第一主信号，以便在对准元件的输出处提供输出步进信号。 该方法包括当两个振荡器信号之间的开关发生时或当检测到第一主信号的故障时引入虚拟步进信号。 该方法还包括在开关的情况下将虚拟步进信号发送到对准元件的输出，直到与新的主信号的对准完成。
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公开(公告)号：US07711875B2
公开(公告)日：2010-05-04
申请号：US12013913
申请日：2008-01-14
申请人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
发明人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
CPC分类号： G06F13/4054
摘要： A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.
摘要翻译： 提供了一种将外部低速工业标准接口转换为片上高速串行链路（HSSL）的转换器装置和方法。 本发明的转换器优选放置在外部接口附近。 HSSL以系统时钟速度运行，因此，HSSL接口信号可以像任何其他定时信号一样轻松处理，便于物理设计过程。 因为在外部接口附近的转换器中执行同步一次，并且沿着本发明的HSSL的信号可以像任何其他定时信号一样被处理，因此消除了对芯片的每个处理元件中的接口单元进行同步的需要。 因此，减少了本发明使用的复杂性和硅面积。 该转换器可实现串行接口的最大速度，这在上电复位，制造测试和芯片调试方面至关重要。
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公开(公告)号：US20090222251A1
公开(公告)日：2009-09-03
申请号：US12347989
申请日：2008-12-31
申请人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack Wayne Riley , Shoji Sawamura , Iwao Takiguchi
发明人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack Wayne Riley , Shoji Sawamura , Iwao Takiguchi
IPC分类号： G06F17/50
CPC分类号： G01R31/318555 , G01R31/318558 , G01R31/318572 , G06F11/2236
摘要： A design structure for a integrated circuit interfacing system may be embodied in a machine readable medium for designing, manufacturing or testing a integrated circuit. In one embodiment, the design structure specifies an integrated circuit that includes multiple interfaces. The design structure may specify that each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. The design structure may also specify a bridge circuit on the integrated circuit that switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.
摘要翻译： 用于集成电路接口系统的设计结构可以体现在用于设计，制造或测试集成电路的机器可读介质中。 在一个实施例中，设计结构指定包括多个接口的集成电路。 设计结构可以指定每个接口耦合到集成电路上相应的一组寄存器或存储元件。 该设计结构还可以指定集成电路上的桥接电路，其可切换地将两个接口耦合在一起，使得一个接口可以与与该接口相关联的寄存器以及与另一接口相关联的寄存器通信。
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公开(公告)号：US20080133800A1
公开(公告)日：2008-06-05
申请号：US12013913
申请日：2008-01-14
申请人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
发明人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
IPC分类号： G06F1/12
CPC分类号： G06F13/4054
摘要： A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.
摘要翻译： 提供了一种将外部低速工业标准接口转换为片上高速串行链路（HSSL）的转换器装置和方法。 本发明的转换器优选放置在外部接口附近。 HSSL以系统时钟速度运行，因此，HSSL接口信号可以像任何其他定时信号一样轻松处理，便于物理设计过程。 因为在外部接口附近的转换器中执行同步一次，并且沿着本发明的HSSL的信号可以像任何其他定时信号一样被处理，因此消除了对芯片的每个处理元件中的接口单元进行同步的需要。 因此，减少了本发明使用的复杂性和硅面积。 该转换器可实现串行接口的最大速度，这在上电复位，制造测试和芯片调试方面至关重要。
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