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    Integrated circuit arrangement having capacitors and having planar transistors and fabrication method
    11.
    发明授权
    Integrated circuit arrangement having capacitors and having planar transistors and fabrication method 有权
    具有电容器并具有平面晶体管和制造方法的集成电路装置

    公开(公告)号：US07173302B2

    公开(公告)日：2007-02-06

    申请号：US10531493

    申请日：2003-10-10

    申请人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    发明人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/1085 ,  H01L21/84 ,  H01L27/10805 ,  H01L27/1203

    摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.

    摘要翻译： 描述了一种集成电路装置及其制造方法。 集成电路装置包含形成电容器的绝缘区域和一系列区域。 该序列包含靠近绝缘区域的近电极区域，电介质区域和远离绝缘区域的远程电极区域。 绝缘区域是布置在平面中的绝缘层的一部分。 电容器和有源部件布置在绝缘层的同一侧上并形成存储单元。 组件的近电极区域和有源区域被布置在与布置绝缘层的平面平行的平面中。 处理器也包含在集成电路装置中。

    Integrated circuit arrangement comprising a capacitor, and production method
    12.
    发明申请
    Integrated circuit arrangement comprising a capacitor, and production method 有权
    包括电容器的集成电路装置和制造方法

    公开(公告)号：US20060003526A1

    公开(公告)日：2006-01-05

    申请号：US10529990

    申请日：2003-10-10

    申请人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rosner ,  Thomas Schulz

    发明人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rosner ,  Thomas Schulz

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1211 ,  H01L27/13 ,  H01L28/60 ,  H01L29/66795

    摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

    摘要翻译： 集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。 电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。 近电极区域是单晶体并且包含多个网状物。 或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。 厚的绝缘区域比控制电极绝缘区域厚。 控制电极含有与远电极区域相同的材料。

    CMOS circuit arrangement
    13.
    发明授权
    CMOS circuit arrangement 有权
    CMOS电路布置

    公开(公告)号：US07342421B2

    公开(公告)日：2008-03-11

    申请号：US10573362

    申请日：2004-09-17

    申请人： Jörg Berthold ,  Ralf Brederlow ,  Christian Pacha ,  Klaus Von Arnim

    发明人： Jörg Berthold ,  Ralf Brederlow ,  Christian Pacha ,  Klaus Von Arnim

    IPC分类号： H03K19/096 ,  H03K19/20

    CPC分类号： H03K19/01728 ,  H01L2924/0002 ,  H03K19/0963 ,  H01L2924/00

    摘要： In an embodiment of the invention, a CMOS circuit arrangement is provided. The CMOS circuit arrangement includes a PMOS logic circuit providing a logic function, having PMOS field effect transistors, wherein a first operating potential is fed to an input of a PMOS logic circuit, an NMOS logic circuit providing the logic function, having NMOS field effect transistors, a first clock transistor, the first source/drain terminal of which is coupled to an input of the NMOS logic circuit, wherein a clock signal is applied to the gate terminal of the first clock transistor, and wherein a second operating potential is fed to the second source/drain terminal. An output of the PMOS logic circuit and an output of the NMOS logic circuit are coupled to one another. Furthermore, an inverter circuit is coupled to the output of the PMOS logic circuit and to the output of the NMOS logic circuit. At least a portion of the NMOS field effect transistors of the NMOS logic circuit have a first threshold voltage and at least a portion of the PMOS field effect transistors of the PMOS logic circuit have a third threshold voltage. The first clock transistor has a second threshold voltage. The first threshold voltage is lower than the second threshold voltage.

    摘要翻译： 在本发明的实施例中，提供了一种CMOS电路装置。 CMOS电路装置包括提供具有PMOS场效应晶体管的逻辑功能的PMOS逻辑电路，其中第一工作电位被馈送到PMOS逻辑电路的输入，提供逻辑功能的NMOS逻辑电路，具有NMOS场效应晶体管 ，第一时钟晶体管，其第一源极/漏极端子耦合到NMOS逻辑电路的输入，其中时钟信号被施加到第一时钟晶体管的栅极端子，并且其中第二工作电位被馈送到 第二源极/漏极端子。 PMOS逻辑电路的输出和NMOS逻辑电路的输出彼此耦合。 此外，逆变器电路耦合到PMOS逻辑电路的输出端和NMOS逻辑电路的输出。 NMOS逻辑电路的NMOS场效应晶体管的至少一部分具有第一阈值电压，PMOS逻辑电路的PMOS场效应晶体管的至少一部分具有第三阈值电压。 第一时钟晶体管具有第二阈值电压。 第一阈值电压低于第二阈值电压。

    Integrated circuit arrangement with capacitor
    14.
    发明授权
    Integrated circuit arrangement with capacitor 有权
    集成电路布置与电容器

    公开(公告)号：US07291877B2

    公开(公告)日：2007-11-06

    申请号：US10529990

    申请日：2003-10-10

    申请人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    发明人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    IPC分类号： H01L29/76

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1211 ,  H01L27/13 ,  H01L28/60 ,  H01L29/66795

    摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

    摘要翻译： 集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。 电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。 近电极区域是单晶体并且包含多个网状物。 或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。 厚的绝缘区域比控制电极绝缘区域厚。 控制电极含有与远电极区域相同的材料。

    Integrated circuit arrangement comprising capacitors and preferably planar transistors, and production method
    18.
    发明申请
    Integrated circuit arrangement comprising capacitors and preferably planar transistors, and production method 有权
    集成电路装置，包括电容器和优选平面晶体管，以及制造方法

    公开(公告)号：US20060022302A1

    公开(公告)日：2006-02-02

    申请号：US10531493

    申请日：2003-10-10

    申请人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rosner ,  Thomas Schulz

    发明人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rosner ,  Thomas Schulz

    IPC分类号： H01L29/00

    CPC分类号： H01L27/1085 ,  H01L21/84 ,  H01L27/10805 ,  H01L27/1203

    摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.

    摘要翻译： 描述了一种集成电路装置及其制造方法。 集成电路装置包含形成电容器的绝缘区域和一系列区域。 该序列包含靠近绝缘区域的近电极区域，电介质区域和远离绝缘区域的远程电极区域。 绝缘区域是布置在平面中的绝缘层的一部分。 电容器和有源部件布置在绝缘层的同一侧上并形成存储单元。 组件的近电极区域和有源区域被布置在与布置绝缘层的平面平行的平面中。 处理器也包含在集成电路装置中。