公开(公告)号：US12229435B2

公开(公告)日：2025-02-18

申请号：US18412731

申请日：2024-01-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/065

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US20240404571A1

公开(公告)日：2024-12-05

申请号：US18646059

申请日：2024-04-25

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G11C7/22

Abstract: In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval. The timing interface receives a data strobe from the control component during the first interval and a data clock from the control component during the second interval, the data strobe departing from a parked voltage level to commence toggling at a time corresponding to reception of the first command/address value, and the data clock toggling throughout the second interval regardless of second command/address value reception-time. The data interface samples first write data corresponding to the first command/address value at times indicated by toggling of the data strobe, and samples second write data corresponding to the second command/address value at times indicated by toggling of the data clock.

公开(公告)号：US20240289047A1

公开(公告)日：2024-08-29

申请号：US18412731

申请日：2024-01-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/065

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G11C7/06 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/0657 ,  G06F2213/16 ,  G11C7/1015 ,  G11C2207/107 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L2225/06541

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US12002506B2

公开(公告)日：2024-06-04

申请号：US17728638

申请日：2022-04-25

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G11C11/00 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G11C11/4093

Abstract: A DRAM device may be configured to retransmit or not retransmit zero or more of command/address signals, write data signals, read data signals, and/or data strobe signals. The DRAM device may have separate, unidirectional read data signal and write data signal interfaces. Combined activate and read or write commands may be implemented. The configuration of the DRAM to retransmit or not retransmit signals may be determined by the DRAM device's physical location on a module via hardwired configuration pins. The various configurations allows a DRAM device to be used on both a long and narrow form factor module and a DIMM module.

公开(公告)号：US11996164B2

公开(公告)日：2024-05-28

申请号：US18216513

申请日：2023-06-29

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C2207/2227

Abstract: Within a memory control component, command/address circuitry transmits a first command/address value to a memory component during a first interval and a second command/address value to the memory component during a second interval, and timing circuitry transmits a data strobe to the memory component during the first interval and a data clock to the memory component during the second interval. The timing circuitry transitions the data strobe from a parked state to a toggling state during the first interval at a predetermined time relative to transmission of the first command/address value and toggles the data clock throughout the second interval regardless of time of transmission of the second command/address value. Data signaling circuitry transmits first write data to the memory component during the first interval synchronously with the write-data strobe signal and transmits second write data to the memory component during the second interval synchronously with the write-data clock signal.

公开(公告)号：US11735237B2

公开(公告)日：2023-08-22

申请号：US17432064

申请日：2020-02-25

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C2207/2227

Abstract: In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval. The timing interface receives a data strobe from the control component during the first interval and a data clock from the control component during the second interval, the data strobe departing from a parked voltage level to commence toggling at a time corresponding to reception of the first command/address value, and the data clock toggling throughout the second interval regardless of second command/address value reception-time. The data interface samples first write data corresponding to the first command/address value at times indicated by toggling of the data strobe, and samples second write data corresponding to the second command/address value at times indicated by toggling of the data clock.

公开(公告)号：US11600316B2

公开(公告)日：2023-03-07

申请号：US17325977

申请日：2021-05-20

Applicant: Rambus Inc.

Inventor： Torsten Partsch ,  John Eric Linstadt ,  Helena Handschuh

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/408

Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.

公开(公告)号：US11900984B2

公开(公告)日：2024-02-13

申请号：US18104069

申请日：2023-01-31

Applicant: Rambus Inc.

Inventor： Torsten Partsch ,  John Eric Linstadt ,  Helena Handschuh

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/408

CPC classification number: G11C11/40626 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.

公开(公告)号：US20250069641A1

公开(公告)日：2025-02-27

申请号：US18810360

申请日：2024-08-20

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Torsten Partsch ,  Wendy Elsasser

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device includes an array of storage cells. Each storage cell is coupled to one of multiple bitlines and one of multiple wordlines. A wordline decoder receives wordline address information and selectively activates an addressed wordline corresponding to the received wordline address information. The wordline decoder includes gating circuitry that is operative during a first mode of operation to selectively suppress activation of the addressed wordline during a refresh operation during a current refresh period based on a timing of an activate command associated with the addressed wordline.

公开(公告)号：US20240394178A1

公开(公告)日：2024-11-28

申请号：US18701574

申请日：2022-10-20

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G06F12/02 ,  G06F13/16 ,  G11C7/10

Abstract: A stacked memory device comprises a stack of dies including respective core memories. An interface die in the stack includes interface circuitry for interfacing between a data bus coupled to a memory controller and the respective core memories of the stack of dies. The interface circuitry may implement decoding of data received from the data bus for the respective core memories and encoding of data sent to the data bus from the respective core memories. The respective core memories of the stacked memory device may be arranged in two or more ranks. A memory module includes a set of stacked memory devices. The stacked memory devices may be arranged in various configurations having varying numbers of channels, ranks, and data widths.